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Error when attempting to make project in Ubuntu

Last post by sslerose « Sun Nov 26, 2023 12:55 am
Replies: 11
by sslerose » Tue Apr 11, 2023 8:56 pm
1

2
11 Replies

5003 Views

Last post by sslerose
Sun Nov 26, 2023 12:55 am
Black Friday 2023 is here!

Last post by redpitaya « Mon Nov 20, 2023 10:50 am

by redpitaya » Mon Nov 20, 2023 10:50 am

0 Replies

717 Views

Last post by redpitaya
Mon Nov 20, 2023 10:50 am
Extract AXI/BRAM Data via Jupyter

Last post by redpitaya « Tue Nov 07, 2023 1:24 pm
Replies: 6
by sslerose » Thu Oct 19, 2023 4:31 am

6 Replies

1396 Views

Last post by redpitaya
Tue Nov 07, 2023 1:24 pm
Running Pavel Demin's FPGA SDR designs under RP OS image (Ubuntu) - repost

Last post by belotserm « Mon Oct 30, 2023 4:44 pm

by belotserm » Mon Oct 30, 2023 4:44 pm

0 Replies

905 Views

Last post by belotserm
Mon Oct 30, 2023 4:44 pm
Lantiq PHY driver for baremetal/standalone

Last post by Andreas80 « Fri Oct 06, 2023 12:43 pm

by Andreas80 » Fri Oct 06, 2023 12:43 pm

0 Replies

36391 Views

Last post by Andreas80
Fri Oct 06, 2023 12:43 pm
DMA problems with new Red Pitaya OS

Last post by redpitaya « Wed Sep 13, 2023 8:36 am
Replies: 6
by Maximilian L » Thu Aug 31, 2023 3:32 pm

6 Replies

2808 Views

Last post by redpitaya
Wed Sep 13, 2023 8:36 am
Issues loading .bit file on FPGA

Last post by juretrn « Tue Sep 05, 2023 8:10 am
Replies: 14
by sourabh-ch » Wed Mar 22, 2023 3:57 pm
1

2
14 Replies

10508 Views

Last post by juretrn
Tue Sep 05, 2023 8:10 am
Event based acquisition using adc_test project

Last post by pavel « Tue Jul 25, 2023 9:59 am
Replies: 1
by Kumblesh_01 » Tue Jul 18, 2023 11:29 am

1 Replies

2360 Views

Last post by pavel
Tue Jul 25, 2023 9:59 am
Extract AXI Stream Data?

Last post by pavel « Thu Jul 20, 2023 10:28 am
Replies: 6
by sslerose » Mon Jul 17, 2023 7:24 pm

6 Replies

2776 Views

Last post by pavel
Thu Jul 20, 2023 10:28 am
Data not being processed by custom Verilog filtering module?

Last post by sslerose « Tue Jul 18, 2023 2:16 am
Replies: 1
by sslerose » Thu Jun 08, 2023 9:23 pm

1 Replies

2470 Views

Last post by sslerose
Tue Jul 18, 2023 2:16 am
Streaming feature not working

Last post by juretrn « Sat Jul 01, 2023 10:35 am
Replies: 1
by arutkeerthi » Fri Jun 30, 2023 3:02 am

1 Replies

2388 Views

Last post by juretrn
Sat Jul 01, 2023 10:35 am
HLS application requiring a memory write to ADC before reading

Last post by nyagaka « Mon Jun 26, 2023 9:31 pm

by nyagaka » Mon Jun 26, 2023 9:31 pm

0 Replies

2200 Views

Last post by nyagaka
Mon Jun 26, 2023 9:31 pm
Using High Level Synthesis streaming blocks with the fast ADCs and DACs

Last post by nyagaka « Wed Jun 14, 2023 4:24 pm

by nyagaka » Wed Jun 14, 2023 4:24 pm

0 Replies

2383 Views

Last post by nyagaka
Wed Jun 14, 2023 4:24 pm
General question about FPGA programming

Last post by juretrn « Wed Jun 14, 2023 1:29 pm
Replies: 1
by ayaqine932001 » Wed Jun 14, 2023 12:28 pm

1 Replies

2422 Views

Last post by juretrn
Wed Jun 14, 2023 1:29 pm
Fast ADC@125MSPS stored at DDR

Last post by beal « Sun Jun 11, 2023 6:53 pm
Replies: 10
by beal » Wed May 10, 2023 1:24 am
1

2
10 Replies

4444 Views

Last post by beal
Sun Jun 11, 2023 6:53 pm
lower voltage at rf output than expected

Last post by nyagaka « Thu Jun 08, 2023 7:55 pm
Replies: 4
by nyagaka » Wed Jun 07, 2023 5:38 pm

4 Replies

2749 Views

Last post by nyagaka
Thu Jun 08, 2023 7:55 pm
FPGA programming to sum two fast signals

Last post by Illia « Thu Jun 08, 2023 10:29 am
Replies: 19
by migibagar » Fri Apr 28, 2023 5:51 pm
1

2
19 Replies

6161 Views

Last post by Illia
Thu Jun 08, 2023 10:29 am
Possibility of Self-Contained Signal Filter Testing on 125-14

Last post by sslerose « Wed Jun 07, 2023 7:30 pm
Replies: 2
by sslerose » Mon Jun 05, 2023 4:42 pm

2 Replies

2517 Views

Last post by sslerose
Wed Jun 07, 2023 7:30 pm
Bare metal ethernet / lwip

Last post by belotserm « Fri May 05, 2023 10:17 pm
Replies: 2
by sgrad » Fri Oct 21, 2022 7:44 am

2 Replies

4319 Views

Last post by belotserm
Fri May 05, 2023 10:17 pm
Getting Started with v0.94_250 FPGA project for SIGNALlab 250-12

Last post by juretrn « Thu May 04, 2023 7:56 am
Replies: 5
by sbenjamin » Tue Apr 18, 2023 2:06 pm

5 Replies

4198 Views

Last post by juretrn
Thu May 04, 2023 7:56 am
Get 20% off SDRlab122-16

Last post by redpitaya « Tue Apr 18, 2023 12:43 pm

by redpitaya » Tue Apr 18, 2023 12:43 pm

0 Replies

2972 Views

Last post by redpitaya
Tue Apr 18, 2023 12:43 pm
Xilinx XADC core

Last post by juretrn « Fri Apr 14, 2023 1:59 pm
Replies: 2
by ansh » Mon Apr 10, 2023 11:56 pm

2 Replies

3329 Views

Last post by juretrn
Fri Apr 14, 2023 1:59 pm
How does the red pitaya implement data acquisition from ADCs

Last post by juretrn « Thu Apr 13, 2023 9:41 am
Replies: 3
by ansh » Tue Apr 11, 2023 9:25 pm

3 Replies

3290 Views

Last post by juretrn
Thu Apr 13, 2023 9:41 am
Fast quadrature signal CORDIC

Last post by redpitaya « Wed Apr 12, 2023 2:34 pm
Replies: 1
by ansh » Fri Apr 07, 2023 8:15 pm

1 Replies

3157 Views

Last post by redpitaya
Wed Apr 12, 2023 2:34 pm
Using the slow DAC from FPGA

Last post by juretrn « Wed Mar 22, 2023 10:38 am
Replies: 4
by fisp » Fri Dec 16, 2022 3:47 pm

4 Replies

4556 Views

Last post by juretrn
Wed Mar 22, 2023 10:38 am

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