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Moving Average on Red Pitaya example

Last post by TheGeri « Wed Aug 28, 2024 1:33 pm
Replies: 7
by TheGeri » Mon Aug 05, 2024 9:21 am

7 Replies

7809 Views

Last post by TheGeri
Wed Aug 28, 2024 1:33 pm
can't make stream_app

Last post by hamza.oncuer « Mon Aug 26, 2024 3:53 pm
Replies: 1
by hamza.oncuer » Thu Aug 22, 2024 8:43 am

1 Replies

1519 Views

Last post by hamza.oncuer
Mon Aug 26, 2024 3:53 pm
Memory write error at 0x100000. MMU section translation fault

Last post by zeroes « Fri Aug 23, 2024 11:39 am

by zeroes » Fri Aug 23, 2024 11:39 am

0 Replies

2549 Views

Last post by zeroes
Fri Aug 23, 2024 11:39 am
Red pitaya exited abnormally

Last post by redpitaya « Thu Jul 25, 2024 3:35 pm
Replies: 3
by zeroes » Tue Jul 23, 2024 10:39 am

3 Replies

9297 Views

Last post by redpitaya
Thu Jul 25, 2024 3:35 pm
send a .c code on the PS Zynq

Last post by redpitaya « Wed Jul 24, 2024 2:40 pm
Replies: 1
by Dnay » Sat Jun 29, 2024 1:38 pm

1 Replies

2894 Views

Last post by redpitaya
Wed Jul 24, 2024 2:40 pm
Multi-FPGA Synchronization on 250-12 for Phase Control

Last post by juretrn « Thu Jun 27, 2024 10:02 am
Replies: 1
by taylor_levaur » Thu Jun 20, 2024 4:36 pm

1 Replies

5167 Views

Last post by juretrn
Thu Jun 27, 2024 10:02 am
Hardware Target Shutdown Error Message

Last post by juretrn « Thu May 30, 2024 12:03 pm
Replies: 1
by bgarrett » Wed May 29, 2024 8:27 pm

1 Replies

3501 Views

Last post by juretrn
Thu May 30, 2024 12:03 pm
Sampled data is always positive

Last post by juretrn « Fri May 17, 2024 9:09 am
Replies: 6
by nyagaka » Tue May 07, 2024 3:55 pm

6 Replies

5509 Views

Last post by juretrn
Fri May 17, 2024 9:09 am
Max number of samples for a FFT in STEMlab 125-14

Last post by juretrn « Fri May 17, 2024 9:00 am
Replies: 5
by javiruni10 » Thu Apr 18, 2024 10:56 am

5 Replies

4776 Views

Last post by juretrn
Fri May 17, 2024 9:00 am
How to go about implementing PGC-ARCTAN

Last post by crrc « Fri May 10, 2024 7:21 am

by crrc » Fri May 10, 2024 7:21 am

0 Replies

3286 Views

Last post by crrc
Fri May 10, 2024 7:21 am
Dividing signals and input to PID

Last post by fpgaSim123 « Thu May 02, 2024 4:27 pm
Replies: 4
by fpgaSim123 » Wed Apr 24, 2024 12:45 pm

4 Replies

8255 Views

Last post by fpgaSim123
Thu May 02, 2024 4:27 pm
Register interaction in v0.94

Last post by sslerose « Tue Apr 30, 2024 5:14 pm
Replies: 5
by sslerose » Wed Mar 27, 2024 3:39 am

5 Replies

11397 Views

Last post by sslerose
Tue Apr 30, 2024 5:14 pm
Output clock constraints

Last post by fbalakirev « Tue Apr 23, 2024 4:57 pm

by fbalakirev » Tue Apr 23, 2024 4:57 pm

0 Replies

3926 Views

Last post by fbalakirev
Tue Apr 23, 2024 4:57 pm
125-14 4CH ADC clocking in PL confusion

Last post by redpitaya « Tue Apr 23, 2024 3:05 pm
Replies: 12
by fbalakirev » Mon Apr 01, 2024 9:09 pm
1

2
12 Replies

13909 Views

Last post by redpitaya
Tue Apr 23, 2024 3:05 pm
ABOUT Socket Communications

Last post by crrc « Wed Apr 17, 2024 6:40 am

by crrc » Wed Apr 17, 2024 6:40 am

0 Replies

3941 Views

Last post by crrc
Wed Apr 17, 2024 6:40 am
ADC data accommodation for FFT IP

Last post by javiruni10 « Thu Apr 11, 2024 4:54 pm
Replies: 2
by javiruni10 » Fri Mar 29, 2024 1:53 am

2 Replies

4448 Views

Last post by javiruni10
Thu Apr 11, 2024 4:54 pm
Modifying v0.94 to Add Functionality in JupyterLab?

Last post by sslerose « Mon Mar 25, 2024 7:55 pm
Replies: 8
by sslerose » Sun Jan 28, 2024 9:06 pm

8 Replies

9297 Views

Last post by sslerose
Mon Mar 25, 2024 7:55 pm
Data misstreatment

Last post by juretrn « Mon Feb 26, 2024 10:59 am
Replies: 2
by javiruni10 » Thu Feb 22, 2024 5:47 pm

2 Replies

4648 Views

Last post by juretrn
Mon Feb 26, 2024 10:59 am
Saving data on SD Card from fpga (Vivado)

Last post by juretrn « Mon Feb 19, 2024 9:39 pm
Replies: 5
by javiruni10 » Fri Feb 16, 2024 10:49 am

5 Replies

5076 Views

Last post by juretrn
Mon Feb 19, 2024 9:39 pm
How "Frequency counter" example works.

Last post by javiruni10 « Fri Feb 16, 2024 10:41 am
Replies: 2
by javiruni10 » Tue Feb 06, 2024 2:30 pm

2 Replies

4603 Views

Last post by javiruni10
Fri Feb 16, 2024 10:41 am
Bare metal ethernet / lwip

Last post by estebangc43 « Mon Feb 12, 2024 3:25 pm
Replies: 3
by sgrad » Fri Oct 21, 2022 7:44 am

3 Replies

19290 Views

Last post by estebangc43
Mon Feb 12, 2024 3:25 pm
ARM and FPGA interaction

Last post by javiruni10 « Tue Feb 06, 2024 2:21 pm
Replies: 2
by javiruni10 » Tue Jan 30, 2024 10:07 am

2 Replies

4975 Views

Last post by javiruni10
Tue Feb 06, 2024 2:21 pm
New Red Pitaya FPGA simulation environment

Last post by juretrn « Sun Jan 28, 2024 11:45 pm

by juretrn » Sun Jan 28, 2024 11:45 pm

0 Replies

4499 Views

Last post by juretrn
Sun Jan 28, 2024 11:45 pm
writing to DDR using AXI-DMA

Last post by juretrn « Tue Jan 23, 2024 7:47 pm
Replies: 1
by nyagaka » Sat Jan 20, 2024 9:47 pm

1 Replies

5476 Views

Last post by juretrn
Tue Jan 23, 2024 7:47 pm
red_pitaya_top.sv (v0.94_250) modification for GPIO usage

Last post by sbenjamin « Sun Jan 07, 2024 5:42 pm
Replies: 9
by sbenjamin » Sun Dec 24, 2023 12:56 pm

9 Replies

9149 Views

Last post by sbenjamin
Sun Jan 07, 2024 5:42 pm

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