FPGA related topics

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Using the slow DAC from FPGA

Last post by juretrn « Wed Mar 22, 2023 10:38 am
Replies: 4
by fisp » Fri Dec 16, 2022 3:47 pm

4 Replies

1097 Views

Last post by juretrn
Wed Mar 22, 2023 10:38 am
122-16 SDR Lab board files

Last post by belotserm « Tue Mar 21, 2023 6:52 pm
Replies: 5
by belotserm » Sun Mar 19, 2023 12:28 am

5 Replies

312 Views

Last post by belotserm
Tue Mar 21, 2023 6:52 pm
Error installing Vitis for Pave Demin's SDR dev environment

Last post by belotserm « Tue Mar 21, 2023 6:31 pm

by belotserm » Tue Mar 21, 2023 6:31 pm

0 Replies

133 Views

Last post by belotserm
Tue Mar 21, 2023 6:31 pm
Bare metal ethernet / lwip

Last post by estebangc43 « Wed Mar 01, 2023 10:47 am
Replies: 1
by sgrad » Fri Oct 21, 2022 7:44 am

1 Replies

912 Views

Last post by estebangc43
Wed Mar 01, 2023 10:47 am
More GPIO

Last post by hamamaher2020 « Thu Feb 16, 2023 5:23 pm
Replies: 3
by hamamaher2020 » Sun Jan 22, 2023 7:49 pm

3 Replies

543 Views

Last post by hamamaher2020
Thu Feb 16, 2023 5:23 pm
MIO pin and DDR memory

Last post by hamamaher2020 « Thu Feb 16, 2023 4:16 pm

by hamamaher2020 » Thu Feb 16, 2023 4:16 pm

0 Replies

251 Views

Last post by hamamaher2020
Thu Feb 16, 2023 4:16 pm
Black Friday 2022 is here!

Last post by redpitaya « Wed Nov 23, 2022 9:32 am

by redpitaya » Wed Nov 23, 2022 9:32 am

0 Replies

660 Views

Last post by redpitaya
Wed Nov 23, 2022 9:32 am
Red Pitaya 125-14: FPGA programming

Last post by juretrn « Fri Nov 18, 2022 8:53 am
Replies: 7
by DrT » Mon Oct 17, 2022 3:01 pm

7 Replies

1521 Views

Last post by juretrn
Fri Nov 18, 2022 8:53 am
Using the Red Pitaya as a pure FPGA

Last post by juretrn « Mon Nov 14, 2022 3:23 pm
Replies: 14
by molinat » Wed Oct 29, 2014 5:31 pm
1

2
14 Replies

14273 Views

Last post by juretrn
Mon Nov 14, 2022 3:23 pm
instructions on Build FPGA

Last post by juretrn « Thu Nov 03, 2022 9:01 am
Replies: 1
by DrT » Wed Nov 02, 2022 4:45 pm

1 Replies

865 Views

Last post by juretrn
Thu Nov 03, 2022 9:01 am
ADC and DAC Gain Select Pins 250-12

Last post by juretrn « Mon Oct 17, 2022 8:42 am
Replies: 3
by taylor_levaur » Thu Oct 13, 2022 5:57 pm

3 Replies

963 Views

Last post by juretrn
Mon Oct 17, 2022 8:42 am
Integrating a Custom FPGA Module with PS/AXI bus

Last post by juretrn « Mon Jul 25, 2022 8:35 am
Replies: 5
by coreyb » Fri Jul 15, 2022 4:45 am

5 Replies

2041 Views

Last post by juretrn
Mon Jul 25, 2022 8:35 am
Using External Signal as clock to DDS in Vivado

Last post by ashish_iuac « Wed Jul 20, 2022 8:19 am

by ashish_iuac » Wed Jul 20, 2022 8:19 am

0 Replies

1124 Views

Last post by ashish_iuac
Wed Jul 20, 2022 8:19 am
“The Zynq Book” a good start, or something more recent advised?

Last post by ph2thet « Wed Jun 22, 2022 2:53 pm
Replies: 3
by ph2thet » Sun Jun 12, 2022 12:01 pm

3 Replies

1490 Views

Last post by ph2thet
Wed Jun 22, 2022 2:53 pm
ERROR in 250-12 Customer Doc

Last post by juretrn « Mon May 09, 2022 8:49 am
Replies: 1
by taylor_levaur » Fri May 06, 2022 6:08 pm

1 Replies

1449 Views

Last post by juretrn
Mon May 09, 2022 8:49 am
Vivado Hardware Manager/ILA Cores

Last post by iamtheweenus « Wed Mar 16, 2022 5:10 pm

by iamtheweenus » Wed Mar 16, 2022 5:10 pm

0 Replies

1513 Views

Last post by iamtheweenus
Wed Mar 16, 2022 5:10 pm
Build a bitstream from Vivado?

Last post by pavel « Mon Feb 14, 2022 9:14 pm
Replies: 1
by f5mzn » Sun Feb 13, 2022 1:03 pm

1 Replies

1678 Views

Last post by pavel
Mon Feb 14, 2022 9:14 pm
constraints files for STEMlab 125-10?

Last post by juretrn « Fri Jan 28, 2022 9:37 am
Replies: 1
by iamtheweenus » Thu Jan 27, 2022 8:21 pm

1 Replies

1861 Views

Last post by juretrn
Fri Jan 28, 2022 9:37 am
Info about the fpga.dts and fpga.dtso files

Last post by opp « Sun Nov 07, 2021 7:31 pm

by opp » Sun Nov 07, 2021 7:31 pm

0 Replies

2163 Views

Last post by opp
Sun Nov 07, 2021 7:31 pm
Vivado version for FPGA programming

Last post by redpitaya « Mon Oct 04, 2021 12:06 pm
Replies: 4
by KSY » Mon Jul 26, 2021 2:57 am

4 Replies

3548 Views

Last post by redpitaya
Mon Oct 04, 2021 12:06 pm
Developing FPGA code using Vivado

Last post by Schrodinger1933 « Mon Jul 06, 2020 11:33 pm

by Schrodinger1933 » Mon Jul 06, 2020 11:33 pm

0 Replies

1954 Views

Last post by Schrodinger1933
Mon Jul 06, 2020 11:33 pm
PB with Vivado Design

Last post by kris13 « Thu Oct 24, 2019 11:58 am
Replies: 1
by kris13 » Tue Oct 22, 2019 4:26 pm

1 Replies

1997 Views

Last post by kris13
Thu Oct 24, 2019 11:58 am
Connecting fpga in Vivado to server

Last post by redpitaya « Thu Oct 03, 2019 2:59 pm
Replies: 1
by vivekh99 » Wed Aug 21, 2019 3:13 pm

1 Replies

2440 Views

Last post by redpitaya
Thu Oct 03, 2019 2:59 pm
Setting up Xilinx Vivado on Ubuntu

Last post by pghalverson « Mon Sep 02, 2019 5:14 pm
Replies: 1
by pghalverson » Thu Aug 15, 2019 6:30 pm

1 Replies

2518 Views

Last post by pghalverson
Mon Sep 02, 2019 5:14 pm
Slow Analog Pin Access in Vivado

Last post by mokbulut « Tue Aug 13, 2019 1:09 pm
Replies: 1
by mokbulut » Mon Aug 12, 2019 3:10 pm

1 Replies

2350 Views

Last post by mokbulut
Tue Aug 13, 2019 1:09 pm

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