FPGA related topics

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FPGA image and Red Pitaya apps

Last post by massimom44 « Fri Dec 06, 2024 11:15 pm
Replies: 15
by massimom44 » Wed Nov 20, 2024 6:07 pm
1

2
15 Replies

1364 Views

Last post by massimom44
Fri Dec 06, 2024 11:15 pm
re-packaging rp_oscilloscope ip

Last post by juretrn « Thu Dec 05, 2024 11:53 am
Replies: 1
by hamza.oncuer » Thu Dec 05, 2024 10:52 am

1 Replies

24 Views

Last post by juretrn
Thu Dec 05, 2024 11:53 am
Starting in RedPitaya

Last post by mem29 « Fri Nov 29, 2024 9:21 pm

by mem29 » Fri Nov 29, 2024 9:21 pm

0 Replies

343 Views

Last post by mem29
Fri Nov 29, 2024 9:21 pm
ERROR while generating bitstream: [DRC PDRC-158] Routing mux contention

Last post by phelkix « Thu Nov 28, 2024 10:51 am
Replies: 2
by phelkix » Tue Nov 26, 2024 4:29 pm

2 Replies

279 Views

Last post by phelkix
Thu Nov 28, 2024 10:51 am
creating overlay device tree

Last post by paracpg « Mon Nov 25, 2024 8:39 pm
Replies: 1
by paracpg » Mon Nov 25, 2024 8:11 pm

1 Replies

227 Views

Last post by paracpg
Mon Nov 25, 2024 8:39 pm
Moving Average on Red Pitaya example

Last post by redpitaya « Tue Oct 29, 2024 1:36 pm
Replies: 13
by TheGeri » Mon Aug 05, 2024 9:21 am
1

2
13 Replies

20681 Views

Last post by redpitaya
Tue Oct 29, 2024 1:36 pm
Pyrpl - custom FPGA code

Last post by juretrn « Wed Oct 23, 2024 9:03 am
Replies: 3
by ikarus » Wed Oct 02, 2024 3:35 pm

3 Replies

3020 Views

Last post by juretrn
Wed Oct 23, 2024 9:03 am
Writing data to DDR3 without PS intervention

Last post by juretrn « Wed Oct 23, 2024 8:45 am
Replies: 4
by prakashbb » Thu Sep 26, 2024 8:02 am

4 Replies

4076 Views

Last post by juretrn
Wed Oct 23, 2024 8:45 am
Problems with stream monitor modport in module 'axi4_stream_cnt'

Last post by fventuri « Thu Oct 17, 2024 1:51 pm

by fventuri » Thu Oct 17, 2024 1:51 pm

0 Replies

2633 Views

Last post by fventuri
Thu Oct 17, 2024 1:51 pm
New Red Pitaya FPGA simulation environment

Last post by juretrn « Thu Oct 17, 2024 11:37 am
Replies: 4
by juretrn » Sun Jan 28, 2024 11:45 pm

4 Replies

8392 Views

Last post by juretrn
Thu Oct 17, 2024 11:37 am
can't make stream_app

Last post by redpitaya « Mon Oct 07, 2024 7:39 am
Replies: 2
by hamza.oncuer » Thu Aug 22, 2024 8:43 am

2 Replies

5314 Views

Last post by redpitaya
Mon Oct 07, 2024 7:39 am
possible change to pyrpl rtl code for iq block

Last post by paracpg « Sat Oct 05, 2024 11:15 am

by paracpg » Sat Oct 05, 2024 11:15 am

0 Replies

3052 Views

Last post by paracpg
Sat Oct 05, 2024 11:15 am
Memory write error at 0x100000. MMU section translation fault

Last post by zeroes « Fri Aug 23, 2024 11:39 am

by zeroes » Fri Aug 23, 2024 11:39 am

0 Replies

9672 Views

Last post by zeroes
Fri Aug 23, 2024 11:39 am
Red pitaya exited abnormally

Last post by redpitaya « Thu Jul 25, 2024 3:35 pm
Replies: 3
by zeroes » Tue Jul 23, 2024 10:39 am

3 Replies

16757 Views

Last post by redpitaya
Thu Jul 25, 2024 3:35 pm
send a .c code on the PS Zynq

Last post by redpitaya « Wed Jul 24, 2024 2:40 pm
Replies: 1
by Dnay » Sat Jun 29, 2024 1:38 pm

1 Replies

6591 Views

Last post by redpitaya
Wed Jul 24, 2024 2:40 pm
Multi-FPGA Synchronization on 250-12 for Phase Control

Last post by juretrn « Thu Jun 27, 2024 10:02 am
Replies: 1
by taylor_levaur » Thu Jun 20, 2024 4:36 pm

1 Replies

12127 Views

Last post by juretrn
Thu Jun 27, 2024 10:02 am
Hardware Target Shutdown Error Message

Last post by juretrn « Thu May 30, 2024 12:03 pm
Replies: 1
by bgarrett » Wed May 29, 2024 8:27 pm

1 Replies

7428 Views

Last post by juretrn
Thu May 30, 2024 12:03 pm
Sampled data is always positive

Last post by juretrn « Fri May 17, 2024 9:09 am
Replies: 6
by nyagaka » Tue May 07, 2024 3:55 pm

6 Replies

9493 Views

Last post by juretrn
Fri May 17, 2024 9:09 am
Max number of samples for a FFT in STEMlab 125-14

Last post by juretrn « Fri May 17, 2024 9:00 am
Replies: 5
by javiruni10 » Thu Apr 18, 2024 10:56 am

5 Replies

8823 Views

Last post by juretrn
Fri May 17, 2024 9:00 am
How to go about implementing PGC-ARCTAN

Last post by crrc « Fri May 10, 2024 7:21 am

by crrc » Fri May 10, 2024 7:21 am

0 Replies

7022 Views

Last post by crrc
Fri May 10, 2024 7:21 am
Dividing signals and input to PID

Last post by fpgaSim123 « Thu May 02, 2024 4:27 pm
Replies: 4
by fpgaSim123 » Wed Apr 24, 2024 12:45 pm

4 Replies

13437 Views

Last post by fpgaSim123
Thu May 02, 2024 4:27 pm
Register interaction in v0.94

Last post by sslerose « Tue Apr 30, 2024 5:14 pm
Replies: 5
by sslerose » Wed Mar 27, 2024 3:39 am

5 Replies

15703 Views

Last post by sslerose
Tue Apr 30, 2024 5:14 pm
Output clock constraints

Last post by fbalakirev « Tue Apr 23, 2024 4:57 pm

by fbalakirev » Tue Apr 23, 2024 4:57 pm

0 Replies

7766 Views

Last post by fbalakirev
Tue Apr 23, 2024 4:57 pm
125-14 4CH ADC clocking in PL confusion

Last post by redpitaya « Tue Apr 23, 2024 3:05 pm
Replies: 12
by fbalakirev » Mon Apr 01, 2024 9:09 pm
1

2
12 Replies

25503 Views

Last post by redpitaya
Tue Apr 23, 2024 3:05 pm
ABOUT Socket Communications

Last post by crrc « Wed Apr 17, 2024 6:40 am

by crrc » Wed Apr 17, 2024 6:40 am

0 Replies

7698 Views

Last post by crrc
Wed Apr 17, 2024 6:40 am

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