FPGA related topics

New Topic

77 topics

Topics

Replies

Views

Last post

Writing data to DDR3 without PS intervention

Last post by prakashbb « Mon Oct 07, 2024 5:53 pm
Replies: 2
by prakashbb » Thu Sep 26, 2024 8:02 am

2 Replies

860 Views

Last post by prakashbb
Mon Oct 07, 2024 5:53 pm
Moving Average on Red Pitaya example

Last post by TheGeri « Mon Oct 07, 2024 1:53 pm
Replies: 10
by TheGeri » Mon Aug 05, 2024 9:21 am
1

2
10 Replies

12737 Views

Last post by TheGeri
Mon Oct 07, 2024 1:53 pm
Pyrpl - custom FPGA code

Last post by redpitaya « Mon Oct 07, 2024 8:08 am
Replies: 1
by ikarus » Wed Oct 02, 2024 3:35 pm

1 Replies

160 Views

Last post by redpitaya
Mon Oct 07, 2024 8:08 am
can't make stream_app

Last post by redpitaya « Mon Oct 07, 2024 7:39 am
Replies: 2
by hamza.oncuer » Thu Aug 22, 2024 8:43 am

2 Replies

2476 Views

Last post by redpitaya
Mon Oct 07, 2024 7:39 am
possible change to pyrpl rtl code for iq block

Last post by paracpg « Sat Oct 05, 2024 11:15 am

by paracpg » Sat Oct 05, 2024 11:15 am

0 Replies

296 Views

Last post by paracpg
Sat Oct 05, 2024 11:15 am
New Red Pitaya FPGA simulation environment

Last post by awmlee « Thu Oct 03, 2024 10:08 pm
Replies: 3
by juretrn » Sun Jan 28, 2024 11:45 pm

3 Replies

5510 Views

Last post by awmlee
Thu Oct 03, 2024 10:08 pm
Memory write error at 0x100000. MMU section translation fault

Last post by zeroes « Fri Aug 23, 2024 11:39 am

by zeroes » Fri Aug 23, 2024 11:39 am

0 Replies

4333 Views

Last post by zeroes
Fri Aug 23, 2024 11:39 am
Red pitaya exited abnormally

Last post by redpitaya « Thu Jul 25, 2024 3:35 pm
Replies: 3
by zeroes » Tue Jul 23, 2024 10:39 am

3 Replies

11175 Views

Last post by redpitaya
Thu Jul 25, 2024 3:35 pm
send a .c code on the PS Zynq

Last post by redpitaya « Wed Jul 24, 2024 2:40 pm
Replies: 1
by Dnay » Sat Jun 29, 2024 1:38 pm

1 Replies

3863 Views

Last post by redpitaya
Wed Jul 24, 2024 2:40 pm
Multi-FPGA Synchronization on 250-12 for Phase Control

Last post by juretrn « Thu Jun 27, 2024 10:02 am
Replies: 1
by taylor_levaur » Thu Jun 20, 2024 4:36 pm

1 Replies

6929 Views

Last post by juretrn
Thu Jun 27, 2024 10:02 am
Hardware Target Shutdown Error Message

Last post by juretrn « Thu May 30, 2024 12:03 pm
Replies: 1
by bgarrett » Wed May 29, 2024 8:27 pm

1 Replies

4471 Views

Last post by juretrn
Thu May 30, 2024 12:03 pm
Sampled data is always positive

Last post by juretrn « Fri May 17, 2024 9:09 am
Replies: 6
by nyagaka » Tue May 07, 2024 3:55 pm

6 Replies

6532 Views

Last post by juretrn
Fri May 17, 2024 9:09 am
Max number of samples for a FFT in STEMlab 125-14

Last post by juretrn « Fri May 17, 2024 9:00 am
Replies: 5
by javiruni10 » Thu Apr 18, 2024 10:56 am

5 Replies

5716 Views

Last post by juretrn
Fri May 17, 2024 9:00 am
How to go about implementing PGC-ARCTAN

Last post by crrc « Fri May 10, 2024 7:21 am

by crrc » Fri May 10, 2024 7:21 am

0 Replies

4225 Views

Last post by crrc
Fri May 10, 2024 7:21 am
Dividing signals and input to PID

Last post by fpgaSim123 « Thu May 02, 2024 4:27 pm
Replies: 4
by fpgaSim123 » Wed Apr 24, 2024 12:45 pm

4 Replies

10140 Views

Last post by fpgaSim123
Thu May 02, 2024 4:27 pm
Register interaction in v0.94

Last post by sslerose « Tue Apr 30, 2024 5:14 pm
Replies: 5
by sslerose » Wed Mar 27, 2024 3:39 am

5 Replies

12759 Views

Last post by sslerose
Tue Apr 30, 2024 5:14 pm
Output clock constraints

Last post by fbalakirev « Tue Apr 23, 2024 4:57 pm

by fbalakirev » Tue Apr 23, 2024 4:57 pm

0 Replies

4870 Views

Last post by fbalakirev
Tue Apr 23, 2024 4:57 pm
125-14 4CH ADC clocking in PL confusion

Last post by redpitaya « Tue Apr 23, 2024 3:05 pm
Replies: 12
by fbalakirev » Mon Apr 01, 2024 9:09 pm
1

2
12 Replies

16621 Views

Last post by redpitaya
Tue Apr 23, 2024 3:05 pm
ABOUT Socket Communications

Last post by crrc « Wed Apr 17, 2024 6:40 am

by crrc » Wed Apr 17, 2024 6:40 am

0 Replies

4902 Views

Last post by crrc
Wed Apr 17, 2024 6:40 am
ADC data accommodation for FFT IP

Last post by javiruni10 « Thu Apr 11, 2024 4:54 pm
Replies: 2
by javiruni10 » Fri Mar 29, 2024 1:53 am

2 Replies

5397 Views

Last post by javiruni10
Thu Apr 11, 2024 4:54 pm
Modifying v0.94 to Add Functionality in JupyterLab?

Last post by sslerose « Mon Mar 25, 2024 7:55 pm
Replies: 8
by sslerose » Sun Jan 28, 2024 9:06 pm

8 Replies

10396 Views

Last post by sslerose
Mon Mar 25, 2024 7:55 pm
Data misstreatment

Last post by juretrn « Mon Feb 26, 2024 10:59 am
Replies: 2
by javiruni10 » Thu Feb 22, 2024 5:47 pm

2 Replies

5634 Views

Last post by juretrn
Mon Feb 26, 2024 10:59 am
Saving data on SD Card from fpga (Vivado)

Last post by juretrn « Mon Feb 19, 2024 9:39 pm
Replies: 5
by javiruni10 » Fri Feb 16, 2024 10:49 am

5 Replies

6153 Views

Last post by juretrn
Mon Feb 19, 2024 9:39 pm
How "Frequency counter" example works.

Last post by javiruni10 « Fri Feb 16, 2024 10:41 am
Replies: 2
by javiruni10 » Tue Feb 06, 2024 2:30 pm

2 Replies

5585 Views

Last post by javiruni10
Fri Feb 16, 2024 10:41 am
Bare metal ethernet / lwip

Last post by estebangc43 « Mon Feb 12, 2024 3:25 pm
Replies: 3
by sgrad » Fri Oct 21, 2022 7:44 am

3 Replies

20328 Views

Last post by estebangc43
Mon Feb 12, 2024 3:25 pm

New Topic

77 topics

Return to Board Index

Who is online

Users browsing this forum: No registered users and 1 guest

Forum permissions

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum