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Real time signal processing

Posted: Wed Jul 29, 2020 9:57 am
by Loes
Hello,

I want to integrate a real time signal processing / pattern recognition.
I am using the 'classic scope + gen' structure as a base.

Eventually I want "my module" to be integrated as follow :

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 *                   /-------\      
 *   PS DDR <------> |  PS   |      AXI <-> custom bus
 *   PS MIO <------> |   /   | <------------+
 *   PS CLK -------> |  ARM  |              |
 *                   \-------/              |
 *                                          |
 *                            /-------\     |
 *                         -> | SCOPE | <---+
 *                         |  \-------/     |
 *                         |                |
 *                         |  /--------\    |
 *                         +->|  MY    | <--+ 
 *                         |  | MODULE |    | 
 *                         |  \--------/    | 
 *                         |         |      |
 *                         |  trig <-+      |
 *                         |                |
 *            /--------\   |   /-----\      |
 *   ADC ---> |        | --+-> |     |      |
 *            | ANALOG |       | PID | <----+
 *   DAC <--- |        | <---- |     |      |
 *            \--------/   ^   \-----/      |
 *                         |                |
 *                         |                | 
 *                         |  /-------\     |
 *                         -- |  ASG  | <---+ 
 *                            \-------/     |
 *                                          |
 *             /--------\                   |
 *    RX ----> |        |                   |
 *   SATA      | DAISY  | <-----------------+
 *    TX <---- |        | 
 *             \--------/ 
 *               |    |
 *               |    |
 *               (FREE)
 
1 - INPUT:
I copied the input signal from the ADCs to be used as input for my module : adc_dat_comp.

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always @(posedge adc_clk)
begin
  adc_dat_raw[0] <= adc_dat_i[0][16-1:2];
  adc_dat_raw[1] <= adc_dat_i[1][16-1:2];
  adc_dat_comp[0] <= adc_dat_i[0][16-1:2];
  adc_dat_comp[1] <= adc_dat_i[1][16-1:2];
end
2 - OUTPUT:
I disconnected one wire from the original design: iobuf_exp_n[0],

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//IOBUF iobuf_exp_n [8-1:0] (.O(gpio.i[23:16]), .IO(exp_n_io), .I(gpio.o[23:16]), .T(gpio.t[23:16]));
IOBUF iobuf_exp_n [8-1:1] (.O(gpio.i[23:17]), .IO(exp_n_io[ 7: 1]), .I(gpio.o[23:17]), .T(gpio.t[23:17]));
and I will use it to send a trigger signal out when the pattern is recognized.

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logic                   my_trigger_out;
assign exp_n_io[0] =    my_trigger_out;
For now the integration looks like that (it will change, but you have the idea):

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red_pitaya_MyModule i_MyModule (
  // ADC
  .adc_a_i       (adc_dat_comp[0]  ),  	// a copy of CH 1 ADC input
  .adc_b_i       (adc_dat_comp[1]  ),  	// a copy of CH 2 ADC input
  .dac_a_i       (asg_dat[0]  ),  		// a copy of CH 1 DAC 
  .dac_b_i       (asg_dat[1]  ),  		// a copy of CH 2 DAC 
  .adc_clk_i     (adc_clk     ),  // clock
  .adc_rstn_i    (adc_rstn    ),  // reset - active low
  .trig_ext_i    (gpio.i[8]   ),  // external trigger
  .trig_asg_i    (trig_asg_out),  // ASG trigger
  .trig_o        (my_trigger_out),
  // System bus
  .sys_addr      (sys[5].addr ),
  .sys_wdata     (sys[5].wdata),
  .sys_wen       (sys[5].wen  ),
  .sys_ren       (sys[5].ren  ),
  .sys_rdata     (sys[5].rdata),
  .sys_err       (sys[5].err  ),
  .sys_ack       (sys[5].ack  )
);
For now I use the scope module to record a trace and the signal generation module to replay it back. A copy of the replay signal get in "my module" and if the replayed signal is greater than my new trace then a trigger signal is sent out.

On the longer run I would like to control this module like the others using a C program.
So I connected this module to the System bus.

Feel free to contact me to discuss this project further.

I would also like to educate myself about the C API and how to modify it so I can control my new module like others (arm, define parameters, read info, ...) with home-made functions.

Cheers,

Re: Real time signal processing

Posted: Thu Jun 02, 2022 8:35 am
by redpitaya
Please note that our APIs and FPGA image code is available on GitHub for free, I think it is best to look at how it is done there and compile or modify it.