Larger capture buffer and clock sync between RPs

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Posts: 28
Joined: Fri Apr 28, 2017 12:43 am

Larger capture buffer and clock sync between RPs

Post by JohnnyMalaria » Sun Aug 13, 2017 8:24 pm

1. Please increase the buffer size significantly from 16K to, say, 1M and/or provide two buffers to allow continuous capture by double buffering.

2. Implement synchronization between RPs. It is possible and has been demonstrated very admirably by Koheron using SATA cables to daisy-chain 4 RPs but it requires a different SD image and steep learning curves (Linux, Vivado, Verilog, FGPA etc etc). This ability is implied by STEMlab but not implemented. Please provide a simple way to switch between internal and external reference clocks. Always supply the actual reference clock via SATA cable to the next RP. Provide a SCPI function to simply select the source. e.g, CLK:INT or CLK:EXT.

The lack of both of these are causing me a lot of frustration and taking a lot of my time to work around. Implementing them would solve all my issues.

I'm sure plenty of other RP owners would support at least one of these requests.


Posts: 17
Joined: Tue Jul 12, 2016 10:34 am

Re: Larger capture buffer and clock sync between RPs

Post by JB » Mon Oct 30, 2017 3:22 pm

Hi Johnny,

while this might not be an official project and still requires a custom SD image, you might have a look at our project at

We are not yet completely finished with all functionalities and you have to solder some resistors to another location for the slave RPs, but in general this project aims at solving your proposals. Changing the clock source via SCPI is impossible with the current hardware since you have to select the clock source physically on the board.

If you have ideas for features, please let us know (or implement them and open a pull request :D )


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