RP and audio DSP
Posted: Mon Mar 12, 2018 7:22 pm
Dear RedPitaya gurus!
I'm new in this forum as well as I'm new with my Red Pitaya (125-14, diagnostic kit). Among using it as a portable oscilloscope, signal generator and logic analyzer I would like the get familiar with basics of FPGA programming.
Quite some time ago, I started my own audio DSP project - digital speaker processor. It is used in a proffesional audio field. It offers amplitude and phase equalisation, splitting audio signals in more frequency bands (crossver), time equalisation and dynamic processing of the sound in terms of protecting speaker units from overload.
Processor is divided in two parts; Analysis part is used for measurement of the speaker system (DUT) and creating a suitable correction filter. Synthesis part performs actual processing in real-time. For amplitude and phase compensation, a special mixed phase FIR filters is used.
System runs on a windows PC and uses computer's CPU for processing. Audio streams are provided with external audio interface(s).
The system runs great in general. From this aspect it would be really nice to implement the synthesis part completely in hardware without the voulnerable PC that compromises robustness of the system.
In consumer digital audio, SPDIF (optical and electrical) is commonly used for transferring digital audio stream between devices. In pro digital audio AES-EBU is commonly used. It is simmilar to SPDIF but it uses balanced line with some higher signal voltages enabling 100-200m of reliable audio connction over shielded balanced cable.
As this protocol is well-known (and the simplest to my mind) I find it the most suitable for my project. SPDIF or AES protocol carry PCM audio samples and the clock signal as well.
I would like to connect SPDIF/AES line to appropriate input of my RP, extract PCM audio samples, process the samples with FIR filter on the FPGA and "write" the resulting audio samples in SPDIF/AES protocol to appropriate output of my RP. There is no AD-DA conversion, everything should go completely digital.
There are commonly 48000 or 96000 samples per channel per second, audio samples have bit depth of 16 or 24 and there are 2 audio channels in SPDIF/AES stream. Compensating FIR filters have 1000-1500 taps in general.
Can anyone give me some suggestion where to start with this project.
Best regards, and thanks for reading/suggesting in this topic.
Kasaudio
I'm new in this forum as well as I'm new with my Red Pitaya (125-14, diagnostic kit). Among using it as a portable oscilloscope, signal generator and logic analyzer I would like the get familiar with basics of FPGA programming.
Quite some time ago, I started my own audio DSP project - digital speaker processor. It is used in a proffesional audio field. It offers amplitude and phase equalisation, splitting audio signals in more frequency bands (crossver), time equalisation and dynamic processing of the sound in terms of protecting speaker units from overload.
Processor is divided in two parts; Analysis part is used for measurement of the speaker system (DUT) and creating a suitable correction filter. Synthesis part performs actual processing in real-time. For amplitude and phase compensation, a special mixed phase FIR filters is used.
System runs on a windows PC and uses computer's CPU for processing. Audio streams are provided with external audio interface(s).
The system runs great in general. From this aspect it would be really nice to implement the synthesis part completely in hardware without the voulnerable PC that compromises robustness of the system.
In consumer digital audio, SPDIF (optical and electrical) is commonly used for transferring digital audio stream between devices. In pro digital audio AES-EBU is commonly used. It is simmilar to SPDIF but it uses balanced line with some higher signal voltages enabling 100-200m of reliable audio connction over shielded balanced cable.
As this protocol is well-known (and the simplest to my mind) I find it the most suitable for my project. SPDIF or AES protocol carry PCM audio samples and the clock signal as well.
I would like to connect SPDIF/AES line to appropriate input of my RP, extract PCM audio samples, process the samples with FIR filter on the FPGA and "write" the resulting audio samples in SPDIF/AES protocol to appropriate output of my RP. There is no AD-DA conversion, everything should go completely digital.
There are commonly 48000 or 96000 samples per channel per second, audio samples have bit depth of 16 or 24 and there are 2 audio channels in SPDIF/AES stream. Compensating FIR filters have 1000-1500 taps in general.
Can anyone give me some suggestion where to start with this project.
Best regards, and thanks for reading/suggesting in this topic.
Kasaudio