SDR (Software Defined Radio) Transceiver

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dvorakvik
Posts: 16
Joined: Fri Sep 26, 2014 9:21 pm

Re: SDR (Software Defined Radio) Transceiver

Post by dvorakvik » Sat Aug 15, 2015 5:57 pm

Wideband active loop antenna .....

http://www.lz1aq.signacor.com/docs/wsml ... ntenna.htm

Regards,

Viktor

fbalakirev
Posts: 41
Joined: Thu Sep 03, 2015 6:56 pm

Re: SDR (Software Defined Radio) Transceiver

Post by fbalakirev » Sat Sep 12, 2015 4:55 pm

Hi Pavel,

What's the correct raw ADC -> volts conversion formula for your design? When I try official RP distro conversion, all negative raw numbers convert to +1V ceiling. If I simply multiply raw i16 values by 1V and divide by 2^13 I get what I would expect. Both cases are in little-endian order. Do I get it right that RP distro encodes ADC recordings differently from your axis_red_pitaya_adc_v1_0 core?

pavel
Posts: 618
Joined: Sat May 23, 2015 5:22 pm

Re: SDR (Software Defined Radio) Transceiver

Post by pavel » Sat Sep 12, 2015 6:58 pm

fbalakirev wrote:Do I get it right that RP distro encodes ADC recordings differently from your axis_red_pitaya_adc_v1_0 core?
The only difference is the sign. There are inverting amplifiers at the inputs and at the outputs of the Red Pitaya board. Initially, axis_red_pitaya_adc_v1_0 returned the ADC samples without inverting them. I've changed it a couple of days ago. Now it returns inverted values as does the default Red Pitaya FPGA configuration.

fbalakirev
Posts: 41
Joined: Thu Sep 03, 2015 6:56 pm

Re: SDR (Software Defined Radio) Transceiver

Post by fbalakirev » Sun Sep 13, 2015 12:56 am

pavel wrote:
The only difference is the sign. There are inverting amplifiers at the inputs and at the outputs of the Red Pitaya board. Initially, axis_red_pitaya_adc_v1_0 returned the ADC samples without inverting them. I've changed it a couple of days ago. Now it returns inverted values as does the default Red Pitaya FPGA configuration.
Hmm, I'm scratching my head now at what I observe on my end.


Here's a side-by-side conversion of a chunk of 0.25 V 7.8125 MHz sine wave I recorded. I print it via:

Code: Select all

 for(i = 0; i < 20; ++i)
  {
    value = *((int16_t *)(ram + 4*i + 2));
    printf("%d\t%f\t%f\n", value,osc_fpga_cnv_cnt_to_v(value,1,0,0),(float)value/(float)0x2000);
  }
Output:

Code: Select all

1302    0.158936        0.158936
671     0.081909        0.081909
-86     1.000000        -0.010498
-819    1.000000        -0.099976
-1438   1.000000        -0.175537
-1843   1.000000        -0.224976
-1998   1.000000        -0.243896
-1868   1.000000        -0.228027
-1462   1.000000        -0.178467
-827    1.000000        -0.100952
-76     1.000000        -0.009277
663     0.080933        0.080933
1270    0.155029        0.155029
1680    0.205078        0.205078
1833    0.223755        0.223755
1696    0.207031        0.207031
1287    0.157104        0.157104
656     0.080078        0.080078
-87     1.000000        -0.010620
-815    1.000000        -0.099487


I wonder if RP core does not pad to 16 same way. Or what else could I be doing wrong? If it were up to me, I'd keep your IP it as it is, since it's a much easier to convert.

pavel
Posts: 618
Joined: Sat May 23, 2015 5:22 pm

Re: SDR (Software Defined Radio) Transceiver

Post by pavel » Sun Sep 13, 2015 12:33 pm

I've never used the osc_fpga_cnv_cnt_to_v function. I've just found its source at:

https://github.com/RedPitaya/RedPitaya/ ... pga.c#L574

I've also checked how the ADC data is registered in the original Red Pitaya FPGA configuration:

https://github.com/RedPitaya/RedPitaya/ ... log.v#L118

Looks like the original Red Pitaya FPGA code does not perform any sign extension and when the 14 bits are converted to 16 or 32 bits, the most significant bits remain 0.

In my axis_red_pitaya_adc core, the sign extension is done at

https://github.com/pavel-demin/red-pita ... _adc.v#L45

In case of the original Red Pitaya code the sign extension is done in osc_fpga_cnv_cnt_to_v.

So, to use osc_fpga_cnv_cnt_to_v with the values returned by my axis_red_pitaya_adc core, the sign extension should be undone by setting the most significant bits to 0. I suppose that something like the following should work:

Code: Select all

osc_fpga_cnv_cnt_to_v(value&0x3fff,1,0,0)
I wonder why you want to use osc_fpga_cnv_cnt_to_v if (float)value/(float)0x2000 works for you.

fbalakirev
Posts: 41
Joined: Thu Sep 03, 2015 6:56 pm

Re: SDR (Software Defined Radio) Transceiver

Post by fbalakirev » Sun Sep 13, 2015 3:46 pm

pavel wrote:
I wonder why you want to use osc_fpga_cnv_cnt_to_v if (float)value/(float)0x2000 works for you.
I just wanted to double check with you what's the correct conversion for your design so I get the voltage right.

pavel
Posts: 618
Joined: Sat May 23, 2015 5:22 pm

Re: SDR (Software Defined Radio) Transceiver

Post by pavel » Sun Sep 13, 2015 6:25 pm

fbalakirev wrote:I just wanted to double check with you what's the correct conversion for your design so I get the voltage right.
I'd say that the most basic expression would be

Code: Select all

max_voltage*(value + zero_offset)/8192.0
If I'm not mistaken, it's what osc_fpga_cnv_cnt_to_v does.

Some applications may require non-linear corrections as for example described in the following application note:
http://www.ti.com/lit/an/slaa050/slaa050.pdf

pavel
Posts: 618
Joined: Sat May 23, 2015 5:22 pm

Re: SDR (Software Defined Radio) Transceiver

Post by pavel » Mon Sep 14, 2015 11:23 pm

Hi,

Recently, I've made some good progress with the development of the Red Pitaya SDR transceiver. It's now dual (2x RX and 2x TX), it works with GNU Radio and will be soon interfaced with the QSDR program. With GNU Radio it can be already used for some experiments and tests.

You can find its description, installation instructions and SD card image at:

http://pavel-demin.github.io/red-pitaya ... ansceiver/

I would be very interested to know if somebody could test this SDR transceiver and post the results.

Cheers,

Pavel

fbalakirev
Posts: 41
Joined: Thu Sep 03, 2015 6:56 pm

Re: SDR (Software Defined Radio) Transceiver

Post by fbalakirev » Tue Sep 15, 2015 3:49 pm

pavel wrote: So, to use osc_fpga_cnv_cnt_to_v with the values returned by my axis_red_pitaya_adc core, the sign extension should be undone by setting the most significant bits to 0. I suppose that something like the following should work:

Code: Select all

osc_fpga_cnv_cnt_to_v(value&0x3fff,1,0,0)
You are correct, osc_fpga_cnv_cnt_to_v(value&0x3fff,1,0,0) output is identical to (float)value/(float)0x2000 .

Do you happen to know how deep are clock converter FIFO in your projects and is there any way to set the depth, besides instantiating AXIS FIFO instead?

pavel
Posts: 618
Joined: Sat May 23, 2015 5:22 pm

Re: SDR (Software Defined Radio) Transceiver

Post by pavel » Tue Sep 15, 2015 8:10 pm

fbalakirev wrote:Do you happen to know how deep are clock converter FIFO in your projects and is there any way to set the depth, besides instantiating AXIS FIFO instead?
The clock converter FIFO depth is 32. It's using AXIS FIFO internally. The FIFO depth is defined by a local parameter P_FIFO_DEPTH in axis_clock_converter_v1_1_axis_clock_converter.v. You can find this file in the sources of your projects:

tmp/*.srcs/sources_1/ipshared/xilinx.com/axis_clock_converter_v1_1/*/hdl/verilog/axis_clock_converter_v1_1_axis_clock_converter.v

If you need a deeper FIFO, then AXIS FIFO is the way to go.

Actually, I don't understand why Xilinx provides both AXIS FIFO and AXIS Clock Converter. If I'm not mistaken, the only difference between these IP cores is that AXIS Clock Converter doesn't let you configure the FIFO depth.

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