FPGA lesson 4 "Frequency counter"

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FPGA lesson 4 "Frequency counter"

Post by Illia » Fri Apr 28, 2023 4:26 pm

Hello everyone.

I am learning to use RedPitaya STEMlab 125-14 board and Vivado environment for my internship and I started with examples posted on RedPitaya knowledge base website.
I had no problems with making and understanding the first three lessons, however working on 4th lesson I have encountered a problem that I can't resolve. The problem concerns the part of executing Python program in Jupiter Notebook - when executing the code I get an error about division by zero, which I suppose comes from this line:

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print("Counts: ", count, " cycles: ",Ncycles, " frequency: ",freq/(count/Ncycles),"Hz\n")
Because the "count" starts from 0 and then there is a division freq/count=freq/0.
And I can't figure out how to resolve this issue.
FYI, I verified that RP does send the signal from OUT1 when using native Signal Generator app and I could observe the sinusoid created by RP with oscilloscope.
So, my guess is that the problem is with the Python code. I will be grateful if someone can help me with this issue.

Thank you in advance.

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Re: FPGA lesson 4 "Frequency counter"

Post by redpitaya » Thu Jun 08, 2023 3:42 pm

Hello Illia,

Sorry for the late reply.

The easiest fix would be to skip the print sentence if the count is 0.

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