Switch off / reduce clockspeed of core

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JoWo1994
Posts: 6
Joined: Wed Jun 13, 2018 4:31 pm

Switch off / reduce clockspeed of core

Post by JoWo1994 » Wed Jun 13, 2018 5:29 pm

Hi,
I currently have some thermal issues with the red pitaya and wondered, if it would be possible to switch off one core (I am not doing too much with it, i mostly use the fpga) or reduce the clock speed of the cores.

I found an forum post that talked about adding the maxcpus=1 to the boot_args of u boot but as I understand it this would result in the core running anyway, just not doing anything.

Am I mistaken here? How would anyone go about switching off a core or reducing their clock frequencies?

JoWo1994
Posts: 6
Joined: Wed Jun 13, 2018 4:31 pm

Re: Switch off / reduce clockspeed of core

Post by JoWo1994 » Thu Jun 14, 2018 11:22 am

Hi again,
I tried to get the red pitaya to only work with one core by adding maxcpus=1 by editing the "u-boot.script" file I found in the patches folder and and recompiling it to get a new u-boot.scr file with the maxcpus argument and the correct checksum (files are attached as txt files).
When I use the originial scr file the red pitaya starts without a problem. When using the modified one which only differs in the maxcpus argument it gets stuck at "Starting kernel ..."

Does anyone have any idea what I could be doing wrong?

Code: Select all


U-Boot 2016.07 (Jan 23 2018 - 20:34:03 +0100)

Model: Red Pitaya Board
Board: Xilinx Zynq
I2C:   ready
DRAM:  ECC disabled 480 MiB
I2C:EEPROM selection failed
MMC:   sdhci@e0100000: 0
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Model: Red Pitaya Board
Board: Xilinx Zynq
Net:   ZYNQ GEM: e000b000, phyaddr 1, interface rgmii-id
eth0: ethernet@e000b000
Hit any key to stop autoboot:  0
Running script from SD...
Device: sdhci@e0100000
Manufacturer ID: 19
OEM: 4459
Name: 00000
Tran Speed: 25000000
Rd Block Len: 512
SD version 1.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
reading u-boot.scr
1213 bytes read in 20 ms (58.6 KiB/s)
## Executing script at 02000000
Set devicetree and ramdisk high loading address to 0x20000000
Loading from SD card (FAT file system) to memory
Device: sdhci@e0100000
Manufacturer ID: 19
OEM: 4459
Name: 00000
Tran Speed: 25000000
Rd Block Len: 512
SD version 1.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
reading uImage
4725072 bytes read in 419 ms (10.8 MiB/s)
reading devicetree.dtb
22582 bytes read in 20 ms (1.1 MiB/s)
Booting Linux kernel with ramdisk and devicetree
## Booting kernel from Legacy Image at 02004000 ...
   Image Name:   Linux-4.4.0-xilinx
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    4725008 Bytes = 4.5 MiB
   Load Address: 00008000
   Entry Point:  00008000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 04000000
   Booting using the fdt blob at 0x4000000
   Loading Kernel Image ... OK
   Loading Device Tree to 1cb3b000, end 1cb43835 ... OK

Starting kernel ...
You do not have the required permissions to view the files attached to this post.

pavel
Posts: 515
Joined: Sat May 23, 2015 5:22 pm

Re: Switch off / reduce clockspeed of core

Post by pavel » Thu Jun 14, 2018 11:48 am

> How would anyone go about switching off a core or reducing their clock frequencies?

I think that stopping one CPU core should be possible using the zynq_remoteproc driver:

https://github.com/Xilinx/linux-xlnx/bl ... moteproc.c

When the driver is loaded, the command to stop the CPU core is

Code: Select all

echo 0 > /sys/devices/soc0/1e000000.remoteproc/remoteproc0/up
However, I'm not sure if it would really reduce the power consumption.

I have a set of patches and instructions that worked for me with Vivado 2015.1:

https://github.com/pavel-demin/red-pita ... metal_test

There is also a forum thread about the zynq_remoteproc driver:

https://forum.redpitaya.com/viewtopic.php?f=14&t=560

JoWo1994
Posts: 6
Joined: Wed Jun 13, 2018 4:31 pm

Re: Switch off / reduce clockspeed of core

Post by JoWo1994 » Thu Jun 14, 2018 11:57 am

Thank you very much

The solution with the additional driver seems a little bit ... complex for what I want to do.

Does anyone have a sd card with this already set up so I can try what effects on the junction temperature switching the core off this way has?

Furthermore I tried using the

Code: Select all

echo 0 >> /sys/devices/system/cpu/cpu1/online
command that was discussed in that post to switch CPU1 off but it only seems to logically disable it and the temperature stays the same.
Last edited by JoWo1994 on Thu Jun 14, 2018 12:18 pm, edited 2 times in total.

JoWo1994
Posts: 6
Joined: Wed Jun 13, 2018 4:31 pm

Re: Switch off / reduce clockspeed of core

Post by JoWo1994 » Thu Jun 14, 2018 11:59 am

Thanks
are there any other ways to reduce the power consumption I might be able to try or should I just invest in some better cooling?

pavel
Posts: 515
Joined: Sat May 23, 2015 5:22 pm

Re: Switch off / reduce clockspeed of core

Post by pavel » Thu Jun 14, 2018 12:13 pm

are there any other ways to reduce the power consumption I might be able to try or should I just invest in some better cooling?
I don't know. I went the "better cooling" route. The heatsink that comes with the Red Pitaya board is underdimentioned. It requires a cooling fan to work properly.

For comparison, the Zynq modules designed by Trenz Electronic come with a more efficient heatsink that works very well with their Zynq modules:

https://shop.trenz-electronic.de/en/TE0 ... tarter-Kit
https://shop.trenz-electronic.de/en/269 ... d-embedded

BTW. Just found an easier way to switch off one of the CPU cores using the CPU hotplug:

https://www.kernel.org/doc/html/v4.14/c ... pu-hotplug

JoWo1994
Posts: 6
Joined: Wed Jun 13, 2018 4:31 pm

Re: Switch off / reduce clockspeed of core

Post by JoWo1994 » Sat Jun 16, 2018 4:37 pm

Small Update:

I confirmed by measuring the current drawn by the Red Pitaya

Code: Select all

echo 0 >> /sys/devices/system/cpu/cpu1/online
has no effect on the power consumption whatsoever.

Furthermore reducing the APUs clock speed was possible via setting
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 in system.tcl from 2 to 8 which reduced the clock speed of the APUs from 666MHz to 166MHz.
This also shoewed up in the BogusMIPS estimations:

Running @ 666MHz:

Code: Select all

root@rp-f055a0:~# cat /proc/cpuinfo
processor       : 0
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 1332.01
Features        : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

processor       : 1
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 1332.01
Features        : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

Hardware        : Xilinx Zynq Platform
Revision        : 0003
Serial          : 0000000000000000
Running @ 166MHz:

Code: Select all

root@rp-f055a0:~# cat /proc/cpuinfo
processor       : 0
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 331.77
Features        : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

processor       : 1
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 331.77
Features        : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

Hardware        : Xilinx Zynq Platform
Revision        : 0003
Serial          : 0000000000000000
But despite this the current drawn dropped only by around 20mA.

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