I am trying to understand how different modules in the Verilog code for V0.92 access the BRAM. I am a little confused as to how the address offset is sent to each module. For example, I know that the house keeping module starts from 0x40000000, scope starts from 0x40100000 and so on so forth. But in the Verilog code, in the scope module, all the addresses are 20 bit and I don't see where the address offset comes in. I also couldn't find this information in the top module. Any help and tips are greatly appreciated! Thanks!
Applications, development tools, FPGA, C, WEB
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