Red Pitaya Block Design with some 'classic' functionality

Applications, development tools, FPGA, C, WEB
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renegade264
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Joined: Mon Apr 08, 2019 1:08 pm

Red Pitaya Block Design with some 'classic' functionality

Post by renegade264 » Fri Oct 11, 2019 2:51 pm

Hi,

I have been using the Red Pitaya for a while now and have developed some applications in c which use the GPIO and the SPI configuration, as defined in the classic FPGA bitstream and it works really well. I am now transitioning over to begin my own FPGA block design which will have this functionality and a lot more (involving the ADC's, DAC's and various FFT's which should be user controllable). I have loaded up the classic project and seen that it is quite resource hungry utilising about 25% of the available logic, I can see that this is spent on various functionality which I dont need, so I've simply commented this out, now I've got the utilisation down to about 3 or 4% and my c applications still work on this bitstream. I am thinking perfect I now just have to slap on my own ADC and DAC block designs based on various other projects and I should be good to go ?

However, simply adding blocks does not work as the .bd file is not at top, red_pitaya_top.sv is. Changing the top obviously doesnt work as the aforementioned file implements a great deal of the logic/wiring in .sv files and through others and relies on this strict hierarchy to do it properly. So I was thinking why not convert the design/project into its own ip and just import that into a new project, I also cant do that since it is written in sv and Vivado does not let you export ip with an sv top, it needs to be in verilog. I've seen some topics online about how to make a verilog wrapper for system verilog, through basically writing your own interface - but I am sceptical about how to implement this as I am worried I will interpret the connections wrongly and mess up the functionality of the system (it would also be very time consuming). If anyone has had success with this or knows how to, do let me know?

I've also tried building up the processing system exactly the same as the classic bitstream, but haven't got so far in this because I am not sure how can mirror the AXI, GPIO and SPI implementation, as a good portion of this is custom wired in sv. (GPIO, I could probably give it a go and get that to work).

I am also unsure about whether using the Xilinx SDK would be a good way to go right about now, before I start really learning about how to use Vivado block design flow properly, I've been keeping an eye on the projects in the community for a couple of years now, mainly Pavel, Anton and Koheron and they seem to have stuck with the block design flow, which I also find quite intuitive, so I am a bit reluctant to consider anything else.

If anyone has any pointers or advice, it would be greatly appreciated!

Best Regards, Renegade

redpitaya
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Re: Red Pitaya Block Design with some 'classic' functionality

Post by redpitaya » Wed Oct 30, 2019 1:44 pm

Hello,
Please try our latest streaming app from the latest beta release. I think it will be easier for you.
You can find the OS img file here: https://redpitaya.readthedocs.io/en/lat ... re-sd-card
And the documentation for it https://redpitaya.readthedocs.io/en/lat ... #streaming.

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renegade264
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Joined: Mon Apr 08, 2019 1:08 pm

Re: Red Pitaya Block Design with some 'classic' functionality

Post by renegade264 » Sat Nov 09, 2019 3:48 pm

Hi,

Thank you for the reply, I will certainly investigate this.

In the meantime I manged to get what I wanted to work, but instead I simply created a new project added the processing system and my own custom IP to buffer the GPIO (n_tri_io and p_tri_io) {this was harder than expected, as there were hierarchy issues, therefore I ended up making my own IP instead of simply an RTL module} , the SPI functionality appeared to work without any changes, just the correct settings in the ps block. I have added the code below so that anyone can use it, quite useful as this enables the use of the GPIO on the rp, with minimal 'borrowing'/hacking and splicing. If the user wants to buffer the LED's for software control, this can be commented back in, I use it as indicators in the PL, therefore it is commented out.

module buffer_gpio(
Inp,
Ou,
Tr,
N_IO,
P_IO
//led_o
);

parameter [24:0] INPUT_WIDTH = 24;
parameter [8:0] OUTPUT_WIDTH = 8;

output [INPUT_WIDTH-1:0] Inp;
input [INPUT_WIDTH-1:0] Ou;
input [INPUT_WIDTH-1:0] Tr;
inout [OUTPUT_WIDTH-1:0] N_IO;
inout [OUTPUT_WIDTH-1:0] P_IO;
//inout [OUTPUT_WIDTH-1:0] led_o;

//IOBUF iobuf_led [8-1:0] (.O(Inp[ 7: 0]), .IO(led_o), .I(Ou[ 7: 0]), .T(Tr[ 7: 0]));
IOBUF iobuf_exp_p [8-1:0] (.O(Inp[15: 8]), .IO(P_IO), .I(Ou[15: 8]), .T(Tr[15: 8]));
IOBUF iobuf_exp_n [8-1:0] (.O(Inp[23:16]), .IO(N_IO), .I(Ou[23:16]), .T(Tr[23:16]));

endmodule


Hope this is useful for people.

Best Regards, Renegade

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