Pb making the bitfile from sources

Applications, development tools, FPGA, C, WEB
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roundround_
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Joined: Sun May 09, 2021 8:17 pm

Pb making the bitfile from sources

Post by roundround_ » Sun May 09, 2021 9:00 pm

Hello,

I have a project for which I have to modify the standard RP_125_14 bitfile a little. So first I wanted to just re-build the bitfile from sources and I already have a problem doing so.

Basically I followed the instructions from this page:
  • Install Vivado 2020.1
  • Clone Redpitaya repository from Github
  • Use the commit related to the last release: v1.04-021
  • Go to the directory /fpga and run

    Code: Select all

    make project PRJ=v0.94
Vivado opens, then I run "Generate Bitstream" and it runs well, it generates a .bit file.
However, when I look at the report generated by Vivado there are multiples errors linked with timing. The first error is that there are invalid statements in the constraint file. I tried to fix it by changing the clock names to something I believed was true, and at least this kind of errors went away. But then there are still timing errors due to negative WNS and TNS values. So for me, even if it generated a .bit file, it cannot be considered as valid.

Does anyone knows how I can generate a valid bitfile? I was considering trying with Vivado 2017 and an older version of the source files, but it is quite time consuming and I was hoping it could work with Vivado 2020.1.

Thanks

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