Fast ADC to DAC multilpication in FPGA

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eforstadt
Posts: 2
Joined: Mon Nov 28, 2022 10:55 pm

Fast ADC to DAC multilpication in FPGA

Post by eforstadt » Mon Nov 28, 2022 11:13 pm

Hi all,

I've been stuck on this problem for a while and was hoping to perhaps get some insight by asking on the forum. I've been using the Red Pitaya for the past couple months, first by SCPI, and now trying to understand how to program in FPGA. I am VERY new to FPGA programming, so would welcome any and all advice.

I am working on creating a signal multiplier with my board. The idea is to capture two signals in IN1 and IN2, multiply them together, and then output the signal through OUT1. The idea is to use the board as a lock-in amplifier, but am starting with just mixing the two signals together first.

I tried creating a Verilog module with the following code: (adapted from https://people.ece.cornell.edu/land/cou ... ckin_amp.v)

Code: Select all

module mixermodule(out1, a, b);
output 		[13:0]	out1;
	input 	signed	[13:0] 	a;
	input 	signed	[13:0] 	b;
	
	wire	signed	[13:0]	out1;
	wire 	signed	[13:0]	mult_out;

	assign mult_out = a * b;
	assign out1 = mult_out[13:0];
	//assign out = {mult_out[35], mult_out[32:16]};
endmodule
I then created a module in the block diagram and connected it as such: https://imgur.com/a/flHqEqM (Was unable to attach an image to the post)

I then ran it, but it wasn't working. Any advice?

Thanks!

juretrn
Posts: 43
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC to DAC multilpication in FPGA

Post by juretrn » Tue Nov 29, 2022 9:04 am

Hi there!
It looks like that in your example, the outputs are registered after the module signed_mult mixer_I/_Q is declared.
Your code is however completely asynchronous. For a DSP block to be instantiated, you need a clock and a reset signal. Without a clock, the Zynq's DSP48 block will not work. Also, the multiplier needs to be of the length that is equal to (size of signal 1) + (size of signal 2). Also, you have to pick the correct scaling of your output. Using the lowest 14 bits will probably not give you a very desirable outcome.

eforstadt
Posts: 2
Joined: Mon Nov 28, 2022 10:55 pm

Re: Fast ADC to DAC multilpication in FPGA

Post by eforstadt » Tue Nov 29, 2022 10:46 pm

Thanks juretrun!

So I tried changing my code to the following:

Code: Select all

module mixer (clk, rst, out1, a, b);
	
	input wire clk; //clock
	input wire rst; //reset
	output 		[27:0]	out1;
	input 	signed	[13:0] 	a;
	input 	signed	[13:0] 	b;
	
	wire	signed	[27:0]	out1;
	wire 	signed	[27:0]	mult_out;

	reg [27:0] multtest;
	assign out1 = multtest;
	
	always @ (posedge clk) begin
	   	if (rst) begin
	       		assign multtest = a * b;
       		end
	end
endmodule
and connected adc_clk_n_i and adc_clk_p_i, to clk and rst, respectively. However, upon synthesizing it, Vivado bombarded me with many error messages. Any suggestions on if there's an issue with how the Verilog code is structured, or if I did not connect the clock and reset correctly?

Thanks again

juretrn
Posts: 43
Joined: Tue Nov 16, 2021 11:38 am

Re: Fast ADC to DAC multilpication in FPGA

Post by juretrn » Wed Nov 30, 2022 9:14 am

Hi,

adc_clk_n/_p are "raw" differential clock signals from the ADC. To use those, you should first use a IBUFDS to turn it into a single-ended clock and then bring it to a PLL or MMCM to make an actual logic clock. A reset must be a single pulse, not a train of pulses.
For the DAC interface, things are more complex, because the interface is DDR, and requires a 125 MHz clock, 250 MHz clock and a 250 MHZ clock phase shifted by 90 degrees.
My suggestion is to use the infrastructure prepared within prj/v0.94/rtl/red_pitaya_top.v because otherwise ADC signals will not be sampled correctly and nothing at all will show up on the DAC.

BTW, reset is usually used like this:

Code: Select all

if(rst)
 signal <= 'h0;
else begin
  signal <= your logic here;
  more logic
  ...
end
I believe we have a basic Verilog course available on the website that you can refer to for these things.

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