Continuous ADC to DAC

[misiara09]

Hello! I am using a Stemlab 125-14 Red Pitaya, and I have a question regarding what I think should be a fairly straightforward problem. I am trying to use the Jupyter Notebook to pass through a wave continuously from the ADC to DAC, and I am struggling with the timing and synchronization of input and output signals. My input signal has a frequency of 1.5 kHz so there is no aliasing. I am getting an output_frequency = input_frequency*decimation/2. Any help to figure out this problem will be greatly appreciated. The code is attached below.

import time
from rp_overlay import overlay
import rp

# Initialize the FPGA and Red Pitaya
fpga = overlay() # Ensure the FPGA overlay is loaded
rp.rp_Init() # Initialize the Red Pitaya

# Configuration parameters
base_sampling_rate = 125e6 # Base sampling rate of 125 MHz
decimation = 100 # Decimation factor
sampling_rate = base_sampling_rate / decimation # Calculate sampling rate using decimation factor
buffer_size = 16384 # Buffer size

# Calculate the time it takes for the buffer to fill
buffer_fill_time = buffer_size / sampling_rate

# Reset Generation and Acquisition
rp.rp_GenReset()
rp.rp_AcqReset()

# Set acquisition parameters for Channel 2
rp.rp_AcqSetDecimation(decimation)
rp.rp_AcqSetTriggerSrc(rp.RP_TRIG_SRC_NOW) # Immediate start

# Set generation parameters for DAC on Channel 2
rp.rp_GenWaveform(rp.RP_CH_2, rp.RP_WAVEFORM_ARBITRARY)
rp.rp_GenOutEnable(rp.RP_CH_2)

# Trigger the generator to start the waveform output
rp.rp_GenTriggerOnly(rp.RP_CH_2)

# Start acquisition on Channel 2
rp.rp_AcqStart()

try:
# Continuous real-time pass-through operation
while True:
# Wait for the buffer to fill based on the calculated time
time.sleep(buffer_fill_time)

# Fetch data from ADC Channel 2
adc_buffer_ch2 = rp.fBuffer(buffer_size)
rp.rp_AcqGetDataV(rp.RP_CH_2, 0, buffer_size, adc_buffer_ch2)

# Directly pass the data to DAC Channel 2 (loopback)
rp.rp_GenArbWaveform(rp.RP_CH_2, adc_buffer_ch2, buffer_size)

# Trigger the generator again to ensure synchronization
rp.rp_GenTriggerOnly(rp.RP_CH_2)

# Free memory by deleting the buffer reference
del adc_buffer_ch2

except KeyboardInterrupt:
# Graceful shutdown on Ctrl+C
print("Pass-through stopped by user.")

finally:
# Release the Red Pitaya resources
rp.rp_Release()
print("Red Pitaya resources released.")

[33dnp]

Hi. You won't be able to do what you want on this FPGA firmware. The generator logic is not suitable for this.

[juretrn]

To elaborate a bit more, you will have to take into account decimation when generating the signal - the generating frequency will have to be reduced by a factor of n_decimation.
That being said, you probably won't like the shape of the signal. The FPGA does not perform interpolation between samples, and thus you will be able to see steps in the signal that will be of the length n_decimation*clock period.

[misiara09]

Thanks! I will try a different approach then.