External clock complications

[matankeda]

Hello,

I am trying to set up a 4CH RP to work with a single-ended external clock.

The specifications on the RP page say that 1-125 MHZ should work, but I am having problems running code at those cycles.

The boot loop appears to go away after ~10 MHZ and I can get some code to work (like blinking the LED), but some don't.

For example, I am trying to run a demanding AXI code with the external clock and cannot get that running at all. At around <10 MHZ it immediately crashes and around >10 MHZ it allocates memory and then crashes.

Am I doing something wrong??

Thank you,
MK

[redpitaya]

Dear MK,

Thank you for writing on the forum.

The external clock specifications are taken from the ADC data sheet. The Red Pitaya FPGA code is tested only for 125 MHz clock, so it is possible the functionality is different at lower external clocks.

The Red Pitaya OS booting sequence reads some parameters from the FPGA at a certain point. If the FPGA is not properly booted, then the OS boot will fail (it is possible to get around this by customizing the OS).