Writing onto Digital outputs

[adam.polak]

Hi Guys!

Due to the fact that PWM signal from slow analog outputs on connector E2 (and being more precise underlying FPGA code driving them) don't mach with my current application, in parallel to digging into FPGA (read: learning from the scratch) I want to try R-2R DAC or maybe some DAC chip to get analog voltage as needed but with use of DO pins on connector E1.

I know how to write the state to the single digital pin but I was wandering if there is a function (I believe there should be) to write whole 'word' - several pins at the same time. If there is one - how many pins can set simultaneously? I would need 9 bit words, which I doubt that will be possible but, at least 8 bit one?

I was trying to find some info about it but or there is no one or I don't know what to look for..

As always - I'll be grateful for any help, suggestions, examples .....
cheers
Adam

[pavel]

Hi Adam,

Why not use the fast DACs?

I've just looked at your initial project description and could not find any mention of the fast DACs. Are they used for something else?

Cheers,

Pavel

[adam.polak]

Hi Pavel,

Well, actually I started with fast channels. Unfortunately there is always ‘but’… I’m using redpitaya for laser based imaging and using analog outputs to drive my scanning system (2 channels – for X and Y scan) and analog input to acquire the data of the image. With fast channels the restriction comes from the 16k size of the buffer and additionally from the frequency I’m operating with. With 16k on buffer I can acquire max 128x128 pixels image per one acquisition (and actually it’s slightly less than 100x100 because with RP on fast channels don’t work very well with low frequency signals and the synchronisation is not perfect therefore I need to discard some signal). This resolution was good to start with but is not good enough at this stage. I tried also other options with fast channels:

- Generating continuous signal on outputs and acquisition of many buffers of data, one after another. To do this though I have to sync 2 redpitayas because in this case I need 3 channels of analog input to collect not only signal of the image but also the positions of the scanner that I can place the data properly while reproducing image. It was doable, but due to this complicated synchronization, the image quality was quite poor and it was very slow process to cover all the parts of the imaged scene – not acceptable.

- I tried to generate signal with fast outputs and acquire with slow inputs. Unfortunately this acquisition is quite slow and fast outputs are not able to generate so low frequency signal that can be synchronized with this acquisition – it just goes to flat DC line – not acceptable.

- I know that here on the forum there is a project about continuous acquisition, but due to the fact that I need to synchronize it with continuous signal generation I gave this idea up – beyond my skills level at this moment.

That’s why I moved to slow DAC’s. Now I’m using a ‘for’ loop with AI and AO for X scan and this is put inside another ‘for’ loop with AO for Y scan – I’m collecting this data into the matrix that is subsequently written to binary file that I’m pulling to Matlab where I can recreate the image. This worked and now I can have image with virtually every resolution – bigger image means just slower scan, but that’s perfectly fine. Unfortunately slow analog channels have other problems in this application. Reading values from analog input is quite slow and it limits speed of acquisition form the start, but I could live with that at this stage. The real problem is the voltage ripple on AO channels. Due to the noise on the voltage fed to my scanning system, but fixed position of pixels coming from my ‘for’ loops scanning method, the acquired image is distorted – simply the voltage on the output is not what my program is putting there. I asked redpitaya support team and they told me that in my case (while setting AO values and reading AI in ‘for’ loops) I’m interrupting reading and writing the register and basically this will not work without rewriting FPGA code. This is beyond my current skill level, and although my intention is to be able to do this, at this moment I’m on the level of going through first blink tutorial – still long way to go I think..

To avoid long delay in my project I thought about using digital outputs to drive external DAC, but here I came to the question as started in this topic – I don’t know if I can write whole words to DO and address few pins simultaneously. I think it should be possible and I could be able to still do it from the level of programming in C.. at least I hope so. If this would work than I could go for R-2R DAC, if not then maybe I will think about some option of setting these pins state one by one and then clocking some DAC chip, but that’s much slower. Actually I don’t know yet it this whole idea will work out – I need 2 analog outputs and I would need 9-bit words for each, but I have only 16 DO pins. I’m thinking if maybe I would be able to somehow share the pins, but I’m still not sure..

Sorry for long story here, but I hope that right now you have better understanding of my project and situation I’m in.. and thank you very much for following the forum and replying on my questions!!!

Cheers
Adam

[pavel]

Hi Adam,

Thanks for the very detailed explanation of your problems.

If I understand well, the main source of these problems is the default FPGA configuration and its API.

So, why not drop the default FPGA configuration and write a custom FPGA configuration that does exactly what is required for your project?

If you're interested, I could help you to write such FPGA configuration.

Do I understand correctly that DACs should output some kind of saw-tooth pulses that could be generated with a counter directly connected to DACs and if ADC buffer is large enough then you only need one ADC channel?

Cheers,

Pavel

[adam.polak]

Hi Pavel!

Yes, indeed the best option would be to write FPGA code specific for this application – it would not only be the logical thing to do (why to add new things if redpitaya can do it already) but also it would keep hardware simple, without adding new components and blocking DO pins that will be useful for something else later on. Therefore I knew that this idea was something temporary until I would be able to get around programming FPGA…

…and now this is the moment when I’m speechless – you propose that you could help me with this code. It would be marvelous if you could do it!! I hope that it wouldn’t take you too much of your time! But if really you could help with that it would not only solve my current problem with its final solution but also it would serve as perfect tutorial for me to study and learn FPGA on it, knowing exactly what it does. Therefore if really you have time and are interested to help me with that I will be very grateful!!! THANK YOU!

Your understanding is basically correct and probably my explanation will always be not very precise because my mind right now is still always working in high level programing language and I believe translating this to FPGA will require somehow different approach. If you don’t mind in a short while I’ll send you an email where I’ll do my best to describe in more detail what is expected from redpitaya to do and I’ll send you my current C code for you to see exactly how I’m getting my current result.

Thank you again!
Adam