What is the recommended Place Design directive?

[tom.zhang]

Hi,

When using Vivado 2013.3 to run implementation, I notice that in the implementation settings there's a section called place design directive, which has many options. I realise that using different directive affects the speed of implementation and I'm wondering which place design directive is recommended for compiling the Verilog code for the Red Pitaya?

[Nils Roos]

The original setting for the 2013.3 placer is 'SpreadLogic_high'. The directive not only affects the speed of implementation, but also the timing closure. Experiment a little, sometimes a failed timing can be resolved with different implementation directives.

[tom.zhang]

Hi Nils,

After the implementation, it shows "Implementation Complete, Failed Timing!". What does that mean?

[Nils Roos]

Very briefly: in a logic circtuit it is important that every signal arrives (and remains stable) at its destination within a certain timeframe - usually from the active clock edge at its origin to the next active clock edge at its destination. The way how the cricuit is placed and routed directly affects the delay each clock and signal experiences on its path. Meeting the timing requirements on every single signal path is called timing closure, and it is fundamentally a large optimization problem that the tools have to solve. "Failed Timing" means that there are one or more signal paths in the implemented design that can not be guaranteed to arrive within their allowed timeframe under all valid operating conditions.

Depending on the number and severity of the timing violations, this could mean that the logic (ie all the signal acquisition and generation functions of the Red Pitaya) will fail to function properly or display erratic behaviour. Mostly, the tools calculate for the worst case, so you might still be ok if there are only a few minor violations.

Hit your preferred search engine up for "timing closure" if you want more details.