Question on the Verilog arithmetics in PID source files

[Ubix2014]

Hi,

I am trying to udertand the source code for the PID block. The red_pitaya_pid_block module has 3 parameters: PSR, ISR and DSR. Do you use them to denote the fraction bits in the fixed-point arithmetics? Otherwise, I can't understand this

kp_reg <= kp_mult[29-1:PSR] ;

However, the set point parameter set_sp_i according to the C-code

{ /* pid_NN_sp - PID NN set-point in [ADC] counts. */
"pid_11_sp", 0, 1, 0, -8192, 8191 },

looks like a number without fraction. The same for the P, I, D coefficients.

Cam someone clarify the purpose of PSR, ISR and DSR parameters?

[Nils Roos]

To me, these parameters look like they are intended to control the relative scaling of the P, I, and D components.

If you follow the logic operations with the given parameters, you will find that in the calculation of the final control value the relative weights of P : I : D are 8 : 1 : 32 - this is a consequence of the number of bits that are used from each multiplication result.
I assume this was done to account for the typical magnitudes of the components for comparable amplification factors (kp, ki, kd) - usually you have derivative < proportional < integral. To put it the other way round, this scaling helps to normalize the respective ranges of the kp, ki, kd values.