Accessing PL from the Python code

[Ubix2014]

Hi,

I am trying to access PL registers from the Python code running on RP

Code: Select all

import sys
from time import sleep
import mmap
import resource

print("LED 1")
print resource.getpagesize()

f = open("/dev/mem", "r+b")

print f.name

mm = mmap.mmap(f.fileno(), 52, offset=0x40000000)

print mm.read_byte()

mm.close()
f.close()

However, I get Bus Error when ever I try to access mm, either with mm.read_byte() or explicitly with mm[48] etc

[Nils Roos]

The reason for the bus error is that the mmapped FPGA registers only support 32bit accesses. The interface logic explicitly generates an error signal if the requested transfer length is not equal to 4 bytes.

It seems the python mmap api can only use byte-sized accesses, so this effectively makes it unusable to interact with the FPGA directly.

[pavel]

I'm using Python to access the PL registers in my embedded SDR project:
https://github.com/pavel-demin/red-pita ... aya_emb.py

The trick is to use mmap together with struct. The following expressions work:

Code: Select all

self.cfg[0:1] = struct.pack('<B', 1)
self.cfg[4:8] = struct.pack('<I', 1)
self.buf[0:4096] = numpy_float_array[0:512].tostring()
result = struct.unpack("<H", self.sts[2:4])[0]

[Ubix2014]

Hi Nils and Pavel,

Using pack helped. I am doing

Code: Select all

mm = mmap.mmap(f.fileno(), 4096, offset=0x40000000)

mm[48:52] = struct.pack('I', 10) 

to control LEDs for example.

The reason for the bus error is that the mmapped FPGA registers only support 32bit accesses. The interface logic explicitly generates an error signal if the requested transfer length is not equal to 4 bytes.

Does this limitation come from the Zync hardware or some interconnect setup? The reason I am asking is that I found this example http://lauri.xn--vsandi-pxa.com/hdl/zyn ... start.html where it is shown how to access the individual bytes on PL

[Nils Roos]

Does this limitation come from the Zync hardware or some interconnect setup? The reason I am asking is that I found this example http://lauri.xn--vsandi-pxa.com/hdl/zyn ... start.html where it is shown how to access the individual bytes on PL

The 32bit limitation is introduced by logic specific to the Red Pitaya (axi_slave.v) that translates the CPU accesses over AXI_GP0 into transactions on the internal sys_* bus-signals.

The interconnects and the AXI_GP0 interface are perfectly capable of performing single byte transfers. In the Red Pitaya there is just no usecase to justify the considerably higher complexity that comes with supporting byte-accesses and unaligned addresses.