Why should input adcs be transformed in red_pitaya_scope.v?

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hokim
Posts: 3
Joined: Sat Jan 30, 2016 4:37 am

Why should input adcs be transformed in red_pitaya_scope.v?

Post by hokim » Mon Apr 25, 2016 2:08 pm

Hi,

Code: Select all

// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
  adc_dat_a <= adc_dat_a_i[16-1:2];
  adc_dat_b <= adc_dat_b_i[16-1:2];
end

// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};

Why should input adcs(adc_dat_a, adc_dat_b) be transformed into 2's complement ?
Is it means that adcs sample inverted input analog voltage(that is, lower voltage corresponds higher input adc value)?
I think if analog voltage isn't inverted, adc_a should be not {adc_dat_a[14-1], ~adc_dat_a[14-2:0]} but {~adc_dat_a[14-1], adc_dat_a[14-2:0]} for signed adc value of 0 at the middle point.
That information is important for my brand new logic on redpitaya hardware.

Thanks in advance

ihfsawls
Posts: 2
Joined: Wed Oct 14, 2020 10:52 am

Re: Why should input adcs be transformed in red_pitaya_scope.v?

Post by ihfsawls » Wed Oct 14, 2020 12:25 pm

I'm also interested in an answer to this.
I believe it is related to viewtopic.php?f=9&t=24711&p=32206&hilit ... ary#p32206 however I can't find a clear answer on the forum.

In the ADCs datasheet (https://www.analog.com/media/en/technic ... 4314fa.pdf) you can find a table of voltage to binary and 2's complement representation. From that I'd assume a bit flip of the MSB was sufficient to get its twos-complement, however in pavel demins ip cores to interface the ADC (and DAC) exactly the opposite is done:

AXIS red pitaya adc:

Code: Select all

 assign m_axis_tdata = {
    {(PADDING_WIDTH+1){int_dat_b_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
    {(PADDING_WIDTH+1){int_dat_a_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_a_reg[ADC_DATA_WIDTH-2:0]};
AXIS red pitaya dac:

Code: Select all

int_dat_a_reg <= {int_dat_a_wire[DAC_DATA_WIDTH-1], ~int_dat_a_wire[DAC_DATA_WIDTH-2:0]};
      int_dat_b_reg <= {int_dat_b_wire[DAC_DATA_WIDTH-1], ~int_dat_b_wire[DAC_DATA_WIDTH-2:0]};
Can someone give clarity on this issue?
Thank you already!

ihfsawls
Posts: 2
Joined: Wed Oct 14, 2020 10:52 am

Re: Why should input adcs be transformed in red_pitaya_scope.v?

Post by ihfsawls » Wed Oct 14, 2020 12:35 pm


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