Why should input adcs be transformed in red_pitaya_scope.v?
Posted: Mon Apr 25, 2016 2:08 pm
Hi,
Why should input adcs(adc_dat_a, adc_dat_b) be transformed into 2's complement ?
Is it means that adcs sample inverted input analog voltage(that is, lower voltage corresponds higher input adc value)?
I think if analog voltage isn't inverted, adc_a should be not {adc_dat_a[14-1], ~adc_dat_a[14-2:0]} but {~adc_dat_a[14-1], adc_dat_a[14-2:0]} for signed adc value of 0 at the middle point.
That information is important for my brand new logic on redpitaya hardware.
Thanks in advance
Code: Select all
// IO block registers should be used here
// lowest 2 bits reserved for 16bit ADC
always @(posedge adc_clk)
begin
adc_dat_a <= adc_dat_a_i[16-1:2];
adc_dat_b <= adc_dat_b_i[16-1:2];
end
// transform into 2's complement (negative slope)
assign adc_a = digital_loop ? dac_a : {adc_dat_a[14-1], ~adc_dat_a[14-2:0]};
assign adc_b = digital_loop ? dac_b : {adc_dat_b[14-1], ~adc_dat_b[14-2:0]};
Is it means that adcs sample inverted input analog voltage(that is, lower voltage corresponds higher input adc value)?
I think if analog voltage isn't inverted, adc_a should be not {adc_dat_a[14-1], ~adc_dat_a[14-2:0]} but {~adc_dat_a[14-1], adc_dat_a[14-2:0]} for signed adc value of 0 at the middle point.
That information is important for my brand new logic on redpitaya hardware.
Thanks in advance