Device tree creating

[JamesW]

Hello,
creating device tree fail with error SwCore device_tree is not found in Repositories.
What is missing?

****** hsi v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source {C:\Users\James\Desktop\fpga\red_pitaya_hsi_dts.tcl}
# set path_sdk C:/Users/James/Desktop/fpga/sdk
# open_hw_design $path_sdk/red_pitaya.sysdef
# set_repo_path C:/Users/James/Desktop/fpga/tmp/device-tree-xlnx-xilinx-v2016.2/
INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
# create_sw_design device-tree -os device_tree -proc ps7_cortexa9_0
ERROR: [Hsi 55-1597] SwCore device_tree is not found in Repositories
ERROR: [Hsi 55-1597] SwCore device_tree is not found in Repositories
ERROR: [Hsi 55-1594] Core device_tree of version not found in repositories
ERROR: [Hsi 55-1447] Error: running create_sw_design.
ERROR: [Common 17-39] 'create_sw_design' failed due to earlier errors.

while executing
"create_sw_design device-tree -os device_tree -proc ps7_cortexa9_0"
(file "C:\Users\James\Desktop\fpga\red_pitaya_hsi_dts.tcl" line 16)
INFO: [Common 17-206] Exiting hsi at Sun Aug 07 15:25:19 2016...

[Nils Roos]

I haven't experimented with building of the new release in Windows, but from the errors I'd guess that some of the previous steps, like downloading and unpacking the devicetree repositories was not finished successfully.

I am not sure a build of the complete project can be done in Windows at all. I suggest you take the recommended route and use ubuntu 16.04 in a virtual machine.

[JamesW]

Thanks.
I didn't build everything , only parts related to FPGA.
You have right. Devicetree repositories was missing. Now it works.

I have another question. I made some changes in FPGA. Where can I found base address of control register?
In old scope is this #define OSC_FPGA_BASE_ADDR 0x40100000. How I can obtain the address?

[Nils Roos]

The address for memory mapped registers is defined by three mechanisms:

1. The AXI GP0 master interface is mapped onto the range 0x40000000-0x7fffffff by this setting

   Code: Select all

   create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces processing_system7/Data] [get_bd_addr_segs M_AXI_GP0/Reg] SEG_system_Reg

2. There is an address decoder in red_pitaya_top.v, which divides this range into blocks of size 0x01000000 each and assigns each segment to one module (hk, scope, pid, ...)
3. in the modules, individual addresses are mapped to registers, eg in housekeeping

[JamesW]

Thanks. It works.