Jitter Noise when decimation factor is 8

Applications, development tools, FPGA, C, WEB
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annik
Posts: 2
Joined: Tue Sep 08, 2015 11:47 am

Jitter Noise when decimation factor is 8

Post by annik » Sat Sep 10, 2016 10:33 am

Hello, Red Pitaya society!
This i my first post on the forum)
I'm working with the signal that is 3.90625 MHz that is 125MHz/32. When I acquire a signal with the decimation factor 1, I geta perfectly stable signal. But as soon as the decimation factor is 8, the acquired signal is very unstabele and i can see jitter. That is my code to acquie the signal:

osc_fpga_set_trigger_delay(snum_total);
g_osc_fpga_reg_mem->data_dec=decimation;

osc_fpga_reset();

g_osc_fpga_reg_mem->cha_thr=osc_fpga_cnv_v_to_cnt(trigger_voltage);
g_osc_fpga_reg_mem->cha_hystersis=osc_fpga_cnv_v_to_cnt(0);
g_osc_fpga_reg_mem->chb_hystersis=osc_fpga_cnv_v_to_cnt(0);
g_osc_fpga_reg_mem->chb_thr=osc_fpga_cnv_v_to_cnt(trigger_voltage);
while(1){
osc_fpga_set_trigger(trigger);
osc_fpga_arm_trigger();
/* Check if the signal has been triggered*/
trig_test=osc_fpga_triggered();
while(trig_test==0)
trig_test=osc_fpga_triggered();
/* Get triggering pointer */
trig_ptr=(g_osc_fpga_reg_mem->wr_ptr_trigger);
}
Thank you a lot for your help!

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