Triggering when decimation factor is 8

Applications, development tools, FPGA, C, WEB
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Triggering when decimation factor is 8

Post by annik » Sat Sep 10, 2016 9:01 pm

Hi to all RedPitaya developers!

I have a problem with the jitter noise when decimation factor is 8. I investigated this problem and defined that the problem comes from triggering. I don't have this problem when the decimation factor is 1. But as soon as the decimation factor is 8, there is a dispersion in triggering (The triggering moment is not perfectly stable).

Is there any reason for this? How can I get rid of jitter noise when decimation factor is 8?

Thank you for your help!

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
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Re: Triggering when decimation factor is 8

Post by Nils Roos » Sun Sep 11, 2016 11:42 pm


in general, the trigger moment is always calculated from the signal as it is processed internally. This means that when operating with decimation factor 8, the trigger will happen when the average over a group of 8 ADC samples crosses the trigger threshold. Naturally, this will always lag behind the actual signal crossing the threshold.
It may also be subject to slight variations because the averaging window is not synchronized to the input waveform, so it may capture a different phase segment each period. These variations are particularly pronounced when the measured signal's frequency is close to the effective sample frequency - at decimation 8, your ~4MHz signal amounts to 4 samples per period. When one averaged sample barely misses to cross the threshold, your trigger moment will shift nearly pi/2 radians with respect to the actual signal.

If you want to avoid this kind of jitter, you will need to maintain a better margin between your measured signal's frequency and the effective sample frequency (=125MHz / decimation).

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