Hi,
I don't find the repitaya sources with the directory FPGA and FPGA2
because I clone the https://github.com/RedPitaya/RedPitaya.git but
in the FPGA directory we can't find the directory ip and the
red_pitaya_vivado_project.tcl doesn't run. In the version with the directory FPGA
and FPGA2 we can find the directory ip in the directory fpga. I don't known if I am clear
Thanks
lates redpitation sources
-
- Posts: 55
- Joined: Tue Mar 01, 2016 1:43 pm
Re: lates redpitation sources
Hi gg38,
from what I know / see in the current repository and from judging the commit messages,
the Red Pitaya FPGA logic has been reorganized in smaller projects, as the FPGA
ressources are limited.
If you take a look at fpga/prj/ you will find the 'classic', 'logic', 'logic_orig', and 'tft' directories
each containing a 'ip' directory.
Take a look at the Makefile line 13 , at fpga/Makefile: 'PRJ ?= logic' defines
a variable passed in line 35 'vivado -source red_pitaya_vivado_project.tcl -tclargs $(PRJ)' to Vivado
to be used in fpga/red_pitaya_vivado.tcl. It's responsible for selecting the 'correct logic' directory,
in this case the 'logic' directory at fpga/prj/.
My suspicion would be that the variable isn't passed correctly. You could try to rewrite the path
in fpga/red_pitaya_vivado.tcl line 8 to 'cd prj/logic' and see how it goes.
This all of course is based on the premises that I guessed correctly
from what I know / see in the current repository and from judging the commit messages,
the Red Pitaya FPGA logic has been reorganized in smaller projects, as the FPGA
ressources are limited.
If you take a look at fpga/prj/ you will find the 'classic', 'logic', 'logic_orig', and 'tft' directories
each containing a 'ip' directory.
Take a look at the Makefile line 13 , at fpga/Makefile: 'PRJ ?= logic' defines
a variable passed in line 35 'vivado -source red_pitaya_vivado_project.tcl -tclargs $(PRJ)' to Vivado
to be used in fpga/red_pitaya_vivado.tcl. It's responsible for selecting the 'correct logic' directory,
in this case the 'logic' directory at fpga/prj/.
My suspicion would be that the variable isn't passed correctly. You could try to rewrite the path
in fpga/red_pitaya_vivado.tcl line 8 to 'cd prj/logic' and see how it goes.
This all of course is based on the premises that I guessed correctly
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