Issue with programming the FPGA

Applications, development tools, FPGA, C, WEB
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jialunluo
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Joined: Fri Sep 09, 2016 3:34 pm

Issue with programming the FPGA

Post by jialunluo » Sat Oct 01, 2016 7:51 pm

Hi all,

I am fairly new to FPGA and I have only dealt with writing Verilog and programming a Digilent Nesys 3 board (that uses a spartan-6 FPGA chip). Red Pitaya is the second but more complicated board I have tried. On Digilent board, I know that I need to generate a bitstream which configures the internal connections of blocks and then the board will function as what you have written. The entire process seems pretty straight forward for what I wanted to do with it.

In contrast, there appears a lot more to the Red Pitaya board. I know that Red Pitaya is a SoC so there is a built-in processor along side an FPGA chip. The processor runs the an image of linux OS provided by red pitaya. (Please correct me if I am wrong on any of these) My first question comes, how do I program the FPGA chip? From what I have Googled, it looks like I generate bitstream and convert it to a binary file with a labtool and load it to the linux system. Then as the LED blink example instructs, I concatenate the file to xdevcfg as in

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cat ~/tmp/fpga.bin > /dev/xdevcfg 
My first question comes: what exactly is the "xdevcfg" file? And how is the FPGA operating along side the OS system? (I guess my question really is: how does the FPGA interface with the linux system?) (Eventually I would like to make use of the fast ADC/DACs to build/modify a PID controller)

Thanks a lot!

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Issue with programming the FPGA

Post by Nils Roos » Sun Oct 02, 2016 7:29 pm

Hi,
what exactly is the "xdevcfg" file?
It is a device driver that encapsulates the internal programming port of the FPGA in a linux character device (a type of device that can be accessed like a file).
My first question comes, how do I program the FPGA chip? From what I have Googled, it looks like I generate bitstream and convert it to a binary file with a labtool and load it to the linux system. Then as the LED blink example instructs, I concatenate the file to xdevcfg
The conversion to bin format with labtool is not neccessary any more, xdevcfg was improved with the ability to accept the Vivado *.bit output directly since then. You can access the FPGA programming port by other means, but the cat... way is the easiest.
And how is the FPGA operating along side the OS system? (I guess my question really is: how does the FPGA interface with the linux system?)
The internal architecture of the ZYNQ SoC provides several points at which the FPGA logic can be mapped into the address space of ARM cores. These come in the form of AXI busses (M_AXI_GP0/1). Then there are some GPIO signals that you can access from the cores and connect to the FPGA internally. And you can access the external DDR memory and the internal OCM memory from the FPGA and exchange data that way.
I believe that covers the main routes.

jialunluo
Posts: 20
Joined: Fri Sep 09, 2016 3:34 pm

Re: Issue with programming the FPGA

Post by jialunluo » Mon Oct 03, 2016 5:18 am

Thank you Nils!

So I went into the git repository and explored around a bit. One of my goals is to use/modify the existing code for the PID app to make a customized PID. I saw some pid related code in RedPitaya/app-free and some SystemVerilog code in RedPitaya/fpga. I am a bit confused as in where should I start looking. How are the codes in RedPitaya/app-free related to those in RedPitaya/fpga?

Nils Roos
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Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Issue with programming the FPGA

Post by Nils Roos » Mon Oct 03, 2016 6:28 pm

The C code in apps-free/scope+pid/src is the server-side (server in this case is the Red Pitaya) code that provides the PID functionality to the "PID Controller & Oscilloscope (0.94-400)" web-app. It depends on the "classic" FPGA configuration, whose Verilog sources and block design can be found in fpga/prj/classic .

jialunluo
Posts: 20
Joined: Fri Sep 09, 2016 3:34 pm

Re: Issue with programming the FPGA

Post by jialunluo » Mon Oct 03, 2016 10:36 pm

Thanks again Nils.

So I want to learn about the building process by first modifying the existing web-app and/or FPGA hardware. I read the "how to make a simple program" page in the wiki, but I have several questions. First, the compilation steps are done in the redpitaya board instead of a PC connecting to the board, right? (But if I want to compile programs on my PC, do I need to do that under linux?)

Second, if I try to make changes in "classic" FPGA configuration, how can I realize it? Will the newly generated bitstream automatically be applied to the FPGA hardware? If not, what are the additional steps I need to take?

Finally, I was trying to find FPGA code or c code that are relevant to the mathematics of manipulating input data from the DAC (for PID) but to no success. Could you point me to the code? Or is it an IP that one cannot but use?

Edit: I just tried to run the .tcl to generate a project by using make in ./RedPitaya/fpga/.

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make project
However I received the following errors:

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ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axis_clock_converter_i1/S_AXIS(system_S_AXI_STR_RX1_aclk) and /S_AXI_STR_RX1(system_S_AXI_STR_RX2_aclk)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /M_AXI_STR_TX1(system_M_AXI_STR_TX1_aclk1) and /axis_clock_converter_o1/M_AXIS(system_M_AXI_STR_TX1_aclk)
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/jl/fpga/RedPitaya/fpga/prj/logic/project/redpitaya.srcs/sources_1/bd/system/system.bd 
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 6241.840 ; gain = 0.004 ; free physical = 113 ; free virtual = 5382
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
I have not created a large project in such extent myself so this error message is not helpful to me. I am using a new clone of the RedPitaya repository. I've been searching the old forum threads for relevant information. I found that there was a RedPitaya project that one could build (I am guessing that it is similar to the result of running the red_pitaya_vivado_project.tcl script). Could you give me a few pointer to set up the project in vivado?

-- Jialun

Nils Roos
Posts: 1441
Joined: Sat Jun 07, 2014 12:49 pm
Location: Königswinter

Re: Issue with programming the FPGA

Post by Nils Roos » Tue Oct 04, 2016 10:13 pm

I just tried to run the .tcl to generate a project by using make in ./RedPitaya/fpga/. However I received the following errors
You need to qualify the target project, like "make PRJ=classic project" or "make PRJ=logic_orig project", because the default for "make" and "make project" is broken at the moment (see also here).

My recommendation for an initial project setup would be to use the "classic" project as a template and modify it according to your needs.
First, the compilation steps are done in the redpitaya board instead of a PC connecting to the board, right? (But if I want to compile programs on my PC, do I need to do that under linux?)
It is possible to compile the dynamic library for a web-app in Windows, but I find it easier to do it in a linux VM or on the Red Pitaya.
Second, if I try to make changes in "classic" FPGA configuration, how can I realize it? Will the newly generated bitstream automatically be applied to the FPGA hardware? If not, what are the additional steps I need to take?
When you have generated a new bitstream, you copy it to the Red Pitaya and load it into the FPGA with "cat ... >/dev/xdefcfg". If you bundle the bitstream with a web-app, there are mechanisms that allow you to configure your bitstream to be loaded automatically when your app is started.
Finally, I was trying to find FPGA code or c code that are relevant to the mathematics of manipulating input data from the DAC (for PID) but to no success. Could you point me to the code? Or is it an IP that one cannot but use?
fpga/prj/classic/rtl/red_pitaya_pid.v and fpga/prj/classic/rtl/red_pitaya_pid_block.v

jialunluo
Posts: 20
Joined: Fri Sep 09, 2016 3:34 pm

Re: Issue with programming the FPGA

Post by jialunluo » Thu Oct 06, 2016 9:16 pm

Thanks Nils! I got it to work now!

Deepthy
Posts: 2
Joined: Fri Sep 14, 2018 10:37 am

Re: Issue with programming the FPGA

Post by Deepthy » Tue Nov 13, 2018 2:25 pm

Hello,
I am trying to reconfigure the fpga such that PID module accepts the setpoint value via input chanel 2, input 1 as PID input variable and ouput 1 as PID output. Setpoint value is directly connected to the dac output 2. I made the corresponding changes in the codes red_pitaya_pid.v, red_pitaya_pid_block.sv and red_pitaya_top.sv. I use a cloned file of the original github repository.
I am quite new to redpitaya and fpga programming stuffs. So my question is
Is it enough to just generate bitstream using vivado, copy the red_pitaya.bit file to the fpga folder in redpitaya sd card and change the fpga.config file in the PID app? Is there any other process I have to do.?

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