Thanks again Nils.
So I want to learn about the building process by first modifying the existing web-app and/or FPGA hardware. I read the "how to make a simple program" page
in the wiki, but I have several questions. First, the compilation steps are done in the redpitaya board instead of a PC connecting to the board, right? (But if I want to compile programs on my PC, do I need to do that under linux?)
Second, if I try to make changes in "classic" FPGA configuration, how can I realize it? Will the newly generated bitstream automatically be applied to the FPGA hardware? If not, what are the additional steps I need to take?
Finally, I was trying to find FPGA code or c code that are relevant to the mathematics of manipulating input data from the DAC (for PID) but to no success. Could you point me to the code? Or is it an IP that one cannot but use?
Edit: I just tried to run the .tcl to generate a project by using make in ./RedPitaya/fpga/.
However I received the following errors:
Code: Select all
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axis_clock_converter_i1/S_AXIS(system_S_AXI_STR_RX1_aclk) and /S_AXI_STR_RX1(system_S_AXI_STR_RX2_aclk)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /M_AXI_STR_TX1(system_M_AXI_STR_TX1_aclk1) and /axis_clock_converter_o1/M_AXIS(system_M_AXI_STR_TX1_aclk)
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/jl/fpga/RedPitaya/fpga/prj/logic/project/redpitaya.srcs/sources_1/bd/system/system.bd
generate_target: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 6241.840 ; gain = 0.004 ; free physical = 113 ; free virtual = 5382
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
I have not created a large project in such extent myself so this error message is not helpful to me. I am using a new clone of the RedPitaya repository. I've been searching the old forum threads for relevant information. I found that there was a RedPitaya project that one could build (I am guessing that it is similar to the result of running the red_pitaya_vivado_project.tcl script). Could you give me a few pointer to set up the project in vivado?