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My first FPGA design
Posted: Thu Dec 15, 2016 2:11 pm
by tsitsimp
Hello,
So, I want to make a design that requires no software; Feed the ADC with 1MHz sine wave, average the signal and feed it to the dac, which is connected to my oscilloscope. The block design I made is attached. Everything runs with a 50 MHz clock. Creating the wrapper and output products, and up to the implementation stage everything is ok, but the bitstream is not generated because it says some ports must be specified to avoid contention, regarding the DAC IP
Code: Select all
ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O standard - 18 out of 148 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of user assigned specific value
Then it says the potential risks of that, a tcl command that overrides this, stressing that it is not recommended and then it states problem ports to be : dac_dat [13:0], dac_wrt, dac_sel, dac_clk, dac_rst
Anyone please could explain what is happening? And also is my design correct as I have perceived it should work?
Johnny
Re: My first FPGA design
Posted: Thu Dec 15, 2016 4:17 pm
by pavel
Hi Johnny,
The ddr_clk port should be connected at a clock twice faster than the main clock. The adc_0/aclk port should be connected to the clock coming from ADC. I can't explain the error message.
Here is a link to a very simple Vivado 2016.3 project with ADC directly connected to DAC:
https://www.dropbox.com/sh/5fy49wae6xwx ... c.zip?dl=1
This project can generate a bitstream file without any error messages.
Best regards,
Pavel
Re: My first FPGA design
Posted: Thu Dec 15, 2016 4:26 pm
by pavel
Feed the ADC with 1MHz sine wave, average the signal and feed it to the dac, which is connected to my oscilloscope.
To average the signal, the easiest solution would be to use the FIR Compiler IP core provided by Xilinx. For example, setting filter coefficients to '0.2, 0.2, 0.2, 0.2, 0.2' would average every five samples.
Re: My first FPGA design
Posted: Fri Dec 16, 2016 3:50 pm
by Nils Roos
Regarding the error message, you probably did not provide constraints definitions where you bind the dac_* output signals to specifically configured device pins.
Re: My first FPGA design
Posted: Sat Nov 25, 2017 9:05 am
by amin
Hi Pavel,
I have been trying your IP block and i got signal response in my DAC1. Here is the output signal as attached below.
[img]
20171125_153754edit.jpg
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but i still not get signal response when i add fir_compiler in IP block.
[img]
photo_2017-11-25_16-41-30.jpg
[/img]
[img]
photo_2017-11-25_16-41-43.jpg
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is there any mistake in my IP block of fir_compiler?
Re: My first FPGA design
Posted: Sat Nov 25, 2017 11:32 am
by pavel
is there any mistake in my IP block of fir_compiler?
The "Filter Options" tab looks OK.
What is in the "Channel Specification" and "Implementation" tabs?
"Number of Paths" should be set to 2. "Input Sampling Frequency" and "Clock Frequency" should be set to 125 MHz.
I'd also suggest to set "Output Rounding Mode" to "Convergent Rounding to Even" and "Output Width" to 16.
Re: My first FPGA design
Posted: Mon Nov 27, 2017 7:28 am
by amin
Pavel,
Thank you for your answer.
I have been using your setting:
"Number of Paths" should be set to 2. "Input Sampling Frequency" and "Clock Frequency" should be set to 125 MHz.
I'd also suggest to set "Output Rounding Mode" to "Convergent Roun
and it is work well.
The next problem is i cannot get output signal from DAC1 when using coefficient FDAtool Matlab .
I am still confused about setting frequency sampling in FDAtool Matlab and FIR compiler.
This is step by step my configuration when using FDAtool matlab and FIR compiler:
Lowpass filter:
fpass= 11 kHz
fcutoff= 12kHz
[img]
fdatool.PNG
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From this FDAtool setting, i got "Num" file that it comes from "File/Export"
[img]
File-export.PNG
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[img]
Numcoefficient.PNG
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This "Num" file for use in coefficient vector in FIR compiler.
[img]
photo_2017-11-27_14-45-36.jpg
[/img]
photo_2017-11-27_14-45-57.jpg
thanks in advance,