Generating Signals - Noisy Second Channel

Applications, development tools, FPGA, C, WEB
Post Reply
Bruno Gama
Posts: 2
Joined: Wed Jul 05, 2017 7:20 pm

Generating Signals - Noisy Second Channel

Post by Bruno Gama » Fri Feb 02, 2018 4:25 pm


I'm developing a sinusoidal signal generator with Red Pitaya. I attached the RLT circuit to help understand what i did.

So, first, i get the 125MHz clock from ADC, this clock goes to Clocking Wizard (clk_wiz_0), the outputs of this block are: 125MHz clock output (clk_out1) and 250MHz clock output (clk_out2), those clocks are 90º dephased.

I use two DDSs to generate the sinusoidal waves, those DDSs are controlled by the PS(design_1).

And we have the DAC_V2 block, that basically drives the signals out to the physical DAC.

The circuit for both channels is exactly the same, but i get the first channel working fine and the second with a lot of noise. See the attached pictures.

Hope someone could help me to figure out why this is happening.
You do not have the required permissions to view the files attached to this post.

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 7 guests