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Generating Signals - Noisy Second Channel

Posted: Fri Feb 02, 2018 4:25 pm
by Bruno Gama
Hi!

I'm developing a sinusoidal signal generator with Red Pitaya. I attached the RLT circuit to help understand what i did.

So, first, i get the 125MHz clock from ADC, this clock goes to Clocking Wizard (clk_wiz_0), the outputs of this block are: 125MHz clock output (clk_out1) and 250MHz clock output (clk_out2), those clocks are 90ยบ dephased.

I use two DDSs to generate the sinusoidal waves, those DDSs are controlled by the PS(design_1).

And we have the DAC_V2 block, that basically drives the signals out to the physical DAC.

The circuit for both channels is exactly the same, but i get the first channel working fine and the second with a lot of noise. See the attached pictures.

Hope someone could help me to figure out why this is happening.