Buffered slow ADC data acquisition

Applications, development tools, FPGA, C, WEB
Post Reply
Posts: 2
Joined: Mon Oct 15, 2018 9:46 am

Buffered slow ADC data acquisition

Post by philippstephan » Mon Oct 15, 2018 10:44 am

Hi, I have a seemingly very basic use case: I want to reverse-engineer a I2C-like protocol with 4 pins. The logic analyzer app does not help much, as the implemented I2C decoder does not match the modified version and the export button is not working. I can't find documentation on the binary dump format.

What I basically want is to have a simple possibility to dump 4 slow pins at the highest sampling rate to analyze the protocol with a deserializer that I'm going to write myself. The next step would be to implement a client for that protocol, so I need to speak I2C-ish fast enough on 4 channels in parallel to communicate. I think this should be possible, correct me if I'm wrong.

Next thing I tried was the jupyter notebook mercury.la example github.com /RedPitaya/jupyter/blob/bf1c9e82062383458361993375bac1f4df45c08e/examples/la_trigger.ipynb. Am I mistaken or is there virtually no documentation? I have no clue what trigger_mask or input_mask are, where the input channels are selected, etc.

Next I turned to SCPI. Unfortunately, after browsing the cluttered documentation thoroughly and judging from forum.redpitaya.com /viewtopic.php?f=11&t=1139&p=29860, the buffered slow ADC functionality is not exposed via the SCPI API. And the thread has not gotten any attention by the manufacturer since 2015. It would be very useful if I could use this API as it would greatly simplify the incorporation into our existing tooling.

So my next approach was to use the C API. As far as I understand it, I will have to provide an FPGA overlay that enables me to access the buffers and set the sampling rate etc. Since I have not worked with FPGA design before, I am having a hard time getting started. I haven't fully worked trough the Vivado intro red-pitaya-fpga-examples.readthedocs.io /en/latest/_downloads/StartprogrammingFPGAusingRedPitayaboard.pdf yet, but it is pretty sparse on the slow ADCs. Shouldn't there be an overlay provided for this use case already? I found github.com /RedPitaya/RedPitaya/blob/master/fpga/tbn/la_trg_tb.sv, but being an absolute beginner, I am by no means certain, nor do I know what to do with it. (My use case seems similar to forum.redpitaya.com /viewtopic.php?f=14&t=2273, but it has not gotten any answer in over a year.) The FPGA documentation rpdocs.readthedocs.io /en/latest/developerGuide/software/fpga.html are really hard to understand for a beginner, I know how to code C, but the red pitaya C documentation redpitaya.readthedocs.io /en/latest/developerGuide/comC.html is… minimalist?!

I am sure I must be missing something here. Where is the documentation on this simple feature? Can someone please point me in the right direction? I have the feeling this basic task should be really easy to accomplish, but I am struggling so badly. The documentation on read the docs or in the source code is very sparse and does not really help me much in most cases. Where can I find the complete handbook or more beginner friendly information? I am sorry if am missing the obvious here, but I spent almost two full days reading the docs and its getting me nowhere. Any help is appreciated.

unfortunatly I'm not allowed to post URLs, so I can't link to the specific documents or post. Sorry for the inconvenience

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 3 guests