Design does not meet timing requirements
Posted: Mon Jul 28, 2014 6:37 pm
Hello,
I just checked out a new version of the software from the git repository, on the master branch
commit: 160fecd0d53dbf7337b67a23dce1557a2533f3d6
and when I compile it with Vivado, I get a critical warning
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
It seems to be the setup constraint on clk_fpga_0.
I've attached what I think the relevant portion of the timing_summary
The problamatic Paths are 61 to 64.
I guess the FPGA is working, it doesn't seem that is affecting normal operation so :S.
Is there any solution to this?
I just checked out a new version of the software from the git repository, on the master branch
commit: 160fecd0d53dbf7337b67a23dce1557a2533f3d6
and when I compile it with Vivado, I get a critical warning
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
It seems to be the setup constraint on clk_fpga_0.
I've attached what I think the relevant portion of the timing_summary
The problamatic Paths are 61 to 64.
I guess the FPGA is working, it doesn't seem that is affecting normal operation so :S.
Is there any solution to this?