Redpitaya Forum

Hello,

I just checked out a new version of the software from the git repository, on the master branch
commit: 160fecd0d53dbf7337b67a23dce1557a2533f3d6

and when I compile it with Vivado, I get a critical warning
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.

It seems to be the setup constraint on clk_fpga_0.
I've attached what I think the relevant portion of the timing_summary
The problamatic Paths are 61 to 64.

I guess the FPGA is working, it doesn't seem that is affecting normal operation so :S.

Is there any solution to this?

I have checked this with our "FPGA genius" , he said that this timings are fine and there is no need to worry about them.

Hi, I try to test a simple modification on FPGA code by having a constant: 16383(which is corresponding to the 14bit DAC data 1) sent to the dac_dat_a_i port in the analog module (in FPGA code), and I used JTAG-USB II to program the FPGA. I saw no output. Is there any codes in software that need to modify to enable the output?

emyemy wrote:Hi, I try to test a simple modification on FPGA code by having a constant: 16383(which is corresponding to the 14bit DAC data 1) sent to the dac_dat_a_i port in the analog module (in FPGA code), and I used JTAG-USB II to program the FPGA. I saw no output. Is there any codes in software that need to modify to enable the output?

This question does not belong in this thread.....

The timing of any design is always depend upon its quality or we can say the timing is depends upon the complexity of design and also depend upon the experience of the designer.