Question about RAM address offset

Applications, development tools, FPGA, C, WEB
Post Reply
blevlab
Posts: 7
Joined: Tue Jul 12, 2016 12:17 am

Question about RAM address offset

Post by blevlab » Thu Jul 18, 2019 3:02 am

Hi,

I am trying to understand how different modules in the Verilog code for V0.92 access the BRAM. I am a little confused as to how the address offset is sent to each module. For example, I know that the house keeping module starts from 0x40000000, scope starts from 0x40100000 and so on so forth. But in the Verilog code, in the scope module, all the addresses are 20 bit and I don't see where the address offset comes in. I also couldn't find this information in the top module. Any help and tips are greatly appreciated! Thanks!

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 3 guests