Changing SPI Mode (SPI_CS_HIGH Flag)
Posted: Thu Jul 18, 2019 7:24 pm
Hi,
I have had great success using the SPI code provided by Red Pitaya from the docs. However I have encountered a situation where I need to change the SPI CS Pin to be active high during run time, as I am interfacing with a number of different SPI devices simultaneously, but consecutively. I have tried to assert the "SPI_CS_HIGH" flag by OR'ing it with the mode, however I get an invalid argument error, this has also been verified with the Spidev_test program (armbedded.taskit.de/node/318).
This leads me to believe that the spi device on board the Red Pitaya does not support this functionality, but it sounds like it shouldn't be impossible to achieve especially since it is connected and controlled by a module in the FPGA (to my understanding), I also see you can add overlays at boot-time, completely re purposing the SPI pins. I am wondering what changes I need to make so that I can change the state of the CS pin on the fly, as setting the flag might suggest? (remapping the CS pin to a gpio is not an option as the system is connected with a plug in header, I also would like a clean solution)
I am running version 0.98, uboot: 2016.4, linux kernel: 2017.2 with the c program loading the 'classic_fpga' bitstream at runtime.
Any help would be much appreciated, Renegade.
I have had great success using the SPI code provided by Red Pitaya from the docs. However I have encountered a situation where I need to change the SPI CS Pin to be active high during run time, as I am interfacing with a number of different SPI devices simultaneously, but consecutively. I have tried to assert the "SPI_CS_HIGH" flag by OR'ing it with the mode, however I get an invalid argument error, this has also been verified with the Spidev_test program (armbedded.taskit.de/node/318).
This leads me to believe that the spi device on board the Red Pitaya does not support this functionality, but it sounds like it shouldn't be impossible to achieve especially since it is connected and controlled by a module in the FPGA (to my understanding), I also see you can add overlays at boot-time, completely re purposing the SPI pins. I am wondering what changes I need to make so that I can change the state of the CS pin on the fly, as setting the flag might suggest? (remapping the CS pin to a gpio is not an option as the system is connected with a plug in header, I also would like a clean solution)
I am running version 0.98, uboot: 2016.4, linux kernel: 2017.2 with the c program loading the 'classic_fpga' bitstream at runtime.
Any help would be much appreciated, Renegade.