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Slow Analog Pin Access in Vivado

Posted: Mon Aug 12, 2019 3:10 pm
by mokbulut

I am new to the Red Pitaya board and FPGA programming (as a disclaimer ;) ). We're working on a project that measures some fluorescence values and does some simple calculations on them.
Currently we have two channels hooked to the fast ADCs and do our processing, but we need a third channel and want to read it via one of the slow analog pins. I've clicked through every Google page now, but I really cannot manage to get the analog pin just showing in my Vivado block diagram. (Essentially I just want the pin showing up like adc_dat_a/b in the Red Pitaya tutorials, so I can connect them to my blocks). I am sure the information is there, but I don't yet understand most of the things. Could someone guide me through the steps in configuring the analog pins (in Vivado)?

Red Pitaya STEM-lab 125-14
Vivado 2019.1
(Please just tell me if you need more info)

Re: Slow Analog Pin Access in Vivado

Posted: Tue Aug 13, 2019 1:09 pm
by mokbulut
Silly me. I found that the pins are already there, named Vaux. For the future users like me: Connect the Vaux pins to the Xilinx XADC IP block, in the configuration of the block select single channel ('Basic' tab, 'Startup channel selection'), change the name of the input in the 'Single Channel' tab to the one you're using. Connect clock pins and rst (make sure the rst is active high^^ see XADC documentation). Also, the Vaux pins are not wired like you would expect, so Vaux0 for example is Analog Input 1 on the E2 connector (actually I found in the ports.xdc the pins are set, is there any reference for the ID's? So which ID is which pin?).