PB with Vivado Design

Applications, development tools, FPGA, C, WEB
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kris13
Posts: 7
Joined: Mon Apr 09, 2018 11:33 pm

PB with Vivado Design

Post by kris13 » Tue Oct 22, 2019 4:26 pm

Hello,

I noticed that when I start a project based on the scripts developed by Pavel Demin, at first everything seems to work correctly.
But as I add or make changes directly from Vivado (version 217.4) I often encounter problems and some features no longer work.
In particular, I often have difficulties with Fifo or BRAM to communicate with the CPU (ARM). I still manage to handle my signals on the DAC or ADC but I can not send any more data to the CPU through fifo or bram.
I will try to switch to the Vivado 218.3 version to try to fix the problem
Did you encounter the same problems? What is the solution ?

kris13
Posts: 7
Joined: Mon Apr 09, 2018 11:33 pm

Re: PB with Vivado Design

Post by kris13 » Thu Oct 24, 2019 11:58 am

Finally I solved the problem by starting from an old configuration. I do not know if the problem comes from a badly configured status register or a slice that has been deleted or something else. Now my configuration is stable on Vivado and I can make my changes but we must remain vigilant because Vivado does not forgive the slightest mistake! Thank you Pavel for your work and all the IP you created.

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