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Hardware Interrupts from PL to PS

Posted: Thu Jul 30, 2020 12:58 pm
by renegade264

I have designed a custom FPGA block design in Vivado and it communicates with a C server running on the Red Pitaya SDR and it is working pretty well, however I have identified two areas of major power usage on the PS side. Firstly I am polling the a finish state in the status register like so

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if ((*sts_flags & 0b00000001) == 0b00000001){
, however this max's out the CPU usage on one core since this statement is in an infinite while loop. Secondly, I have the other CPU core in a different thread, probing the network socket to see if control packets are available, this is also in quite an inefficient while loop with a usleep statement:

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go = recv(sock_client, cmd_recv, RECV_PCKT_SIZE, MSG_DONTWAIT);
, therefore my total PS CPU usage it at 100%. I have experimented with the flags on the recv function but I haven't had much luck, I will continue to look into this and post the result. Either way my C program works and everything works as expected for the most, I am just unsatisfied with the two while loops and polling setup.

Nevertheless, my main question is how can I setup hardware interrupts from the PL to PS, in total I will have 4 interrupt signals to map. From reading this: ... o/uio.html I am guessing I will have to make some modifications to the device tree and Kernel, having a browse through the vivado interface I see this section in PS configuration (attached), I guess I will also have to modify my design to route through the GPIO rather than the sts register. I have also read a lot the posts regarding interrupts on this forum. So I am wondering what exactly do I need to do to setup hardware interrupts before I embark on quite a big adventure to attempt this and secondly, if anyone has actually done it from the PL to PS successfully?

Best Regards, Ren