Clock Jitter determination and reduction

Applications, development tools, FPGA, C, WEB
Post Reply
Posts: 1
Joined: Mon Sep 07, 2020 1:49 pm

Clock Jitter determination and reduction

Post by vahishta31 » Mon Sep 07, 2020 2:01 pm


I have implemented RP into a radar module I am working on. In this setup the ADC and DAC need to be as synchronized as possible. I have used a PLL in Vivado and connected the ADC clock to it to generate a 125 MHz clock which is driving both ADC and DAC IP in my software. Now my question is, how can I determine the existing jitter? I am comparing my module with a DAQ unit I have from NI which is 12 bits. Theoretically with 14 bits RP I should get a better SNR in my radar signal, but I don't and the signal seems to change a lot and not stable. Before coming to conclusion that the performance of RP is not good enough compared to the NI DAQ card, I want to check if the clock jitter is negligible and the synchronization between DAC and ADC. When I connect IN and OUT directly to each other and watch the signal, it seems stable but still there is around -/+20 digitized units difference between consecutive radar signals.


Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: Google [Bot] and 1 guest