Maximize sampling of slow Analog Inputs

Applications, development tools, FPGA, C, WEB
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ToBe
Posts: 2
Joined: Sun Jul 25, 2021 12:42 pm

Maximize sampling of slow Analog Inputs

Post by ToBe » Sun Jul 25, 2021 1:02 pm

Hi Forum,

i'm working on a quiet simple piece of code and can't get it to work properly. I want to sample 3 independent Signals @ the slow AIN Ports with a sampling rate of at least 1 ksps.
To get started, i've used the "4.read_voltage_graph" example of the git repo.

As far as i understand, the controller CPP:
- samples every "SIGNAL_UPDATE_INTERVAL" milliseconds
- pushes the value in the vector of the size "SIGNAL_SIZE_DEFAULT" (FIFO style)
- then completely overrides the Signal "VOLTAGE" with the new Vector by using a for loop over "SIGNAL_SIZE_DEFAULT"

So my first question here: is this the way this works or am i getting something wrong here?
If i'm right here: isn't it a little unefficient that the whole Vector is copied to the SIGNAL every time a new Sample is acquired?

The thing is, when only streaming one Signal to the WebApp, everthing seems to be fine, scaling the code to stream 3 Signals, each signal seem to have a much lower Sampling rate.

So i really want to speed up the controller to deliver true 1ksps per channel.

Is there a elegant solution? I also thought about a custom fpga image, but I think it should be feasable to get this done with the standard application, right?

Thank you in advance! :)

Kind regards
Tony

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redpitaya
Site Admin
Posts: 535
Joined: Wed Mar 26, 2014 7:04 pm

Re: Maximize sampling of slow Analog Inputs

Post by redpitaya » Thu Aug 12, 2021 11:03 am

I recommend you to start from a working example on our github repository and modify according to your project needs.

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