SIGNALlab 250-12 idelay purpose and configuration

Applications, development tools, FPGA, C, WEB
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SIGNALlab 250-12 idelay purpose and configuration

Post by rjthomas » Mon Oct 25, 2021 7:20 am

I'm writing HDL code for a custom FPGA image for the SIGNALlab 250-12 board, and I am confused about the purpose of the IDELAYE2 components found in the input stages for the ADC data in the file (approximately lines 418 to 472 under v0.94_250/rtl_250). I assume that the purpose of these delay components is to account for differential delays in the different PCB traces connecting the ADC chip to the FPGA. Is this correct?

Much more importantly, the IDELAYE2 components each have three inputs idly_ce, idly_inc, and idly_rst for each ADC bit which are set by the operating system through the housekeeping module (memory addresses 0x40000044 to 0x4000004C). Are these signals used at all? When and how are they set? I've tried to trace the operation of the scope+generator web app, and especially the initialization and setup phases, but I haven't had any success.

My underlying problem is that the values I extract from the ADCs using a VHDL version of the ADC input code are both very close to zero even when a definite voltage is applied to the ADCs. I'm clearly doing something wrong, and the only mysterious part of the input stages for the ADCs are the IDELAYE2 components and how they are configured.

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