Hello everyone,
I am working on a project where I wish to drive the analog pins on extension connector two via PL code. Based on the constraints file in Pavel's projects, I have some idea as to what code I would have to add and where- add the appropriate "set_property" statements for the ports in the xdc file to characterize the ports, and then write statements to create the ports in the tcl script that configures the ports for the project. Where I am getting stuck is, according to the red pity documentation for the extension connectors (https://redpitaya.readthedocs.io/en/lat ... xtent.html), there is not an associated FPGA pin number for the analog I/O in extension connector two. Any help to access these I/O ports programmatically is appreciated.
Accessing the Analog I/O pins in Extension Connector 2 via FPGA
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Re: Accessing the Analog I/O pins in Extension Connector 2 via FPGA
Slow analog outputs are driven by PDM outputs from FPGA.
This is visible in the schematic:
https://downloads.redpitaya.com/doc//Re ... v1.0.1.pdf
AO0 -> AOF0 , etc.
This is visible in the schematic:
https://downloads.redpitaya.com/doc//Re ... v1.0.1.pdf
AO0 -> AOF0 , etc.
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