Redpitaya Forum

The fast Redpitaya input works well, till the decimation is lower than DEC=131072 (2^17).

Is there a software problem or higher decimation is not implemented yet?
The RedPitaya documentation on link: https://redpitaya.readthedocs.io/en/lat ... decimation
Says: "The table lists only a few decimation examples, users can in practice use any whole decimation value >=1."
Is there a way to implement higher decimation factors in fast ADC input?

Julijan, JSI

The current FPGA implementation supports 17 bit decimation values. Expanding these bitwidths would require also expanding the entire following DSP chain.

So basically Decimation 131072 should work?

131071 is the maximum decimation value.