Read fast ADC - Decimation (131072)

Applications, development tools, FPGA, C, WEB
Post Reply
julijanp
Posts: 2
Joined: Tue Nov 22, 2022 10:24 am

Read fast ADC - Decimation (131072)

Post by julijanp » Tue Nov 22, 2022 10:34 am

The fast Redpitaya input works well, till the decimation is lower than DEC=131072 (2^17).

Is there a software problem or higher decimation is not implemented yet?
The RedPitaya documentation on link: https://redpitaya.readthedocs.io/en/lat ... decimation
Says: "The table lists only a few decimation examples, users can in practice use any whole decimation value >=1."
Is there a way to implement higher decimation factors in fast ADC input?

Julijan, JSI

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Read fast ADC - Decimation (131072)

Post by juretrn » Tue Nov 22, 2022 10:47 am

The current FPGA implementation supports 17 bit decimation values. Expanding these bitwidths would require also expanding the entire following DSP chain.

julijanp
Posts: 2
Joined: Tue Nov 22, 2022 10:24 am

Re: Read fast ADC - Decimation (131072)

Post by julijanp » Tue Nov 22, 2022 10:52 am

So basically Decimation 131072 should work?

juretrn
Posts: 104
Joined: Tue Nov 16, 2021 11:38 am

Re: Read fast ADC - Decimation (131072)

Post by juretrn » Tue Nov 22, 2022 1:55 pm

131071 is the maximum decimation value.

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 23 guests