Sweep sine with sine

[ThomasGobmaier]

Hi,
for a mechanical system I have to sweep a sine wave between two frequencies.
The source code has RP_GEN_SWEEP_MODE_LINEAR and RP_GEN_SWEEP_MODE_LOG.

But I would need RP_GEN_SWEEP_MODE_SINE so the variation between the
start- and endfrequency varies with a slow sine and not linear or log.

The sweep should run between 60 Hz and 70 Hz each second.

Is there a way to do this with software or has the FPGA to be programmed to support this?

[juretrn]

There is no official support for such a feature, unfortunately. Perhaps you could hack the current implementation by setting the DAC step register quickly, but I am not sure how quick that setting can be.
For a proper implementation, you would probably need a second DAC sample table within FPGA that could be used to load up additional information for signal generation.