Generation of a signal from a trigger

[TheGeri]

Hello everyone! I am new to working with the Red Pitaya, and I have a question:

I am currently using the Red Pitaya 125-14 with SCPI commands and Python. I have a generator function connected to input 1 of the Red Pitaya, which continuously generates pulses. The idea is that when the Red Pitaya detects a voltage rise above a certain threshold, it activates the digital signal DIO0_P.

When I use the oscilloscope, I can see that the digital signal activates every time I run the program. However, the issue is that the signal activation occurs at a different time compared to the rising signal for each run of the programme I do.

I have attached the code:

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#!/usr/bin/env python3

import sys
import time
import redpitaya_scpi as scpi

#Setup the connection to the Red Pitaya
rp_s = scpi.scpi(sys.argv[1])

# RST on GEN and DIG
rp_s.tx_txt('DIG:RST')
rp_s.tx_txt('ACQ:RST')

# DIO0_P as output
rp_s.tx_txt('DIG:PIN:DIR OUT,DIO0_P')

# Acquisition
rp_s.tx_txt('ACQ:TRIG:LEV 0.5')
rp_s.tx_txt('ACQ:TRIG:DLY 0')
rp_s.tx_txt('ACQ:DEC 1')

rp_s.tx_txt('ACQ:START')
time.sleep(0.1)
rp_s.tx_txt('ACQ:TRIG CH1_PE')
rp_s.tx_txt('DIG:PIN DIO0_P,1')

# Wait for trigger
while 1:
    rp_s.tx_txt('ACQ:TRIG:STAT?')           # Get Trigger Status
    if rp_s.rx_txt() == 'TD':  
      break
      

I would appreciate it if someone could review it and offer any possible solutions to the issue. Thank you all in advance

[redpitaya]

Hello TheGeri,

Thank you for writing to us. I apologise for the late reply.

The easy way to do it would be to change the DIO0_P to 1 after the acquisition trigger has been achieved.

This will only happen one time of course. If you want it to happen multiple times, you will have to create a for loop or something similar that starts acquisition multiple times.

Please note that if the acquisition condition is not met, the program will never exit (while loop).

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#!/usr/bin/env python3

import sys
import time
import redpitaya_scpi as scpi

#Setup the connection to the Red Pitaya

IP = 'rp-f066c8.local'
rp_s = scpi.scpi(IP)

# RST on GEN and DIG
rp_s.tx_txt('DIG:RST')
rp_s.tx_txt('ACQ:RST')

# DIO0_P as output
rp_s.tx_txt('DIG:PIN:DIR OUT,DIO0_P')

# Acquisition
rp_s.tx_txt('ACQ:TRIG:LEV 0.5')
# rp_s.tx_txt('ACQ:TRIG:DLY 0')  #! Default setting
# rp_s.tx_txt('ACQ:DEC 1')      #! Default setting

rp_s.tx_txt('ACQ:START')
time.sleep(0.1)
rp_s.tx_txt('ACQ:TRIG CH1_PE')

# Wait for trigger
while 1:
    rp_s.tx_txt('ACQ:TRIG:STAT?')           # Get Trigger Status
    if rp_s.rx_txt() == 'TD':  
      break

# The while loop will not exit unless the trigger condition is met

rp_s.tx_txt('DIG:PIN DIO0_P,1')

[redpitaya]

I also added some quality-of-life improvements, so that the board IP does not have to be typed in every time the program starts.

Before the modification the DIO0_P would be turned ON regardless of the state of the acquisition (the command was placed before the trigger condition was met)

[TheGeri]

Hello,

Thanks for your reply and the improved SCPI connection code.

Using your code, when I active the program ang generate a single pulse with the function generator on input 1 (pink colour on the oscilloscope), I observe that the DIO0_P signal (green colour) is activated at different times relative to the pulse.

You can see 3 examples here: https://postimg.cc/gallery/cZVsTr2

My goal is that the DIO0_P signal is activated immediately after the trigger is activated. Any advice?

Thanks very much in advance

Kind regards,

[redpitaya]

Hello TheGeri,

A constant/relative delay of DIO0_P (or any GPIO for that matter) is going to be hard to achieve through Python. In the background, Red Pitaya needs some time to process the request and the Linux OS on the Red Pitaya is non-real time.

The best way to achieve the immediate delay would be to reprogram the FPGA (checking for a rising edge on fast analog inputs and turning ON the DIO0_P when the condition is met).

Here is a project that might be helpful to you (the 0.94 project on the site is meant for 1.04-28 Red Pitaya OS):
https://lniv.fe.uni-lj.si/redpitaya/
But you can use the same principles to reprogram the FPGA for the OS version you are currently using.

Alternatively, you can try to create a C program that runs on the Red Pitaya itself. That should improve the delay and the relative delay. This will be faster than Python, but slower than FPGA.

Best regards

[TheGeri]

Good afternoon,

First of all, thank you very much for your response and the link you provided! I have followed the steps outlined here: https://redpitaya-knowledge-base.readth ... v/top.html. I have installed Vivado version 2020.1 and I am working with the Windows Subsystem for Linux on Ubuntu version 18.04.06 LTS.

When following the example from here https://redpitaya-knowledge-base.readth ... fpga2.html, right after synthesizing in Vivado, the application closes, and I receive this response in the command prompt:

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make project PRJ=v0.94 MODEL=Z10
vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 ""

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

start_gui
Abnormal program termination (11)
Please check '/home/ciurana/RedPitaya-FPGA/prj/v0.94/hs_err_pid19432.log' for details
segfault in /Opt/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/vivado -exec vivado -source red_pitaya_vivado_project_Z10.tcl -tclargs v0.94 , exiting...
Makefile:47: recipe for target 'project' failed
make: *** [project] Error 139

The error file states the following:

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#
# An unexpected error has occurred (11)
#
Stack:
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib//server/libjvm.so(+0xb6aadb) [0x7ff9b25d6adb]
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib//server/libjvm.so(JVM_handle_linux_signal+0xbb) [0x7ff9b25dbe1b]
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib//server/libjvm.so(+0xb647b8) [0x7ff9b25d07b8]
/lib/x86_64-linux-gnu/libc.so.6(+0x3ef10) [0x7ffa039a5f10]
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib/libawt_xawt.so(+0x47f79) [0x7ff98cf0df79]
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib/libawt_xawt.so(+0x485b2) [0x7ff98cf0e5b2]
/Opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib/libawt_xawt.so(Java_sun_awt_X11_XRobotPeer_getRGBPixelsImpl+0x30d) [0x7ff98cefefdd]
[0x7ff99a8fd99e]

I've been researching, but I haven't been able to resolve this issue. Do you have any ideas on how to solve it? Thank you very much in advance ."

[TheGeri]

Hello, I just wanted to mention that using the command

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/vivado &

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~/vivado$
****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

start_gui

I launched the Vivados programm and I generated the bitstream without any problem. However, using PuTTY and following the commands provided in the tutorials:

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scp red_pitaya_top.bit root@rp-xxxxxx.local:/root
cat /root/red_pitaya_top.bit > /dev/xdevcfg

I followed the LED blink example, and after executing this final command (cat /root...) (I've made sure that there is a copy of the "red_pitaya_top.bit" in the root directory). I couldn't observe any LED blinking, and I am unsure why this is happening. I would greatly appreciate any assitance or guidance in resolving this issue. Thanks!

[redpitaya]

Hello TheGeri,

I will check this out.

If you are using the 2.00 OS version, I apologise. I thought that the 2.00 FGPA update was already applied to the tutorials, however, I double-checked and noticed that I forgot to merge it with the main branch. Anyway, the tutorials should be updated for the 2.00 OS now:
https://redpitaya-knowledge-base.readth ... s/top.html

[TheGeri]

Good afternoon,

Thank you very much for your response! I have used the following commands, following the new tutorial (version 2.00 OS - I have this version on my RP board):

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cd <Path/to/RedPitaya/repository>/prj/v0.94/project/repitaya.runs/impl_1
echo -n "all:{ red_pitaya_top.bit }" >  red_pitaya_top.bif
bootgen -image red_pitaya_top.bif -arch zynq -process_bitstream bin -o red_pitaya_top.bit.bin -w

And I receive the following:

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"bootgen: command not found."

Do you know what I might be doing wrong?

[TheGeri]

Good afternoon,

It's working now, and I see the LED blinking . Updating the PATH in the bashrc was necessary.

Thanks for your help!!