Thanks a ton for your reply!
I use OS 1.04 version and while there I could get PID running with PyRPL (after making some changes in the code). I would just like to divide signals and send it to the PID module.
First Question:
I have attempted replacing the PID module with a custom 'adder'' that uses the same register space (please see below) and adds input 1 and input 2. I would like to now try division but the modification from '+' to '/' does not work:
Code: Select all
division: process(dat_a_i,dat_b_i)
begin
dat_a_o <= dat_a_i / dat_b_i ;
end process;
How can I do the division? I get the error:
found '0' definitions of the operator "/".
I even tried using the IEEE.NUMERIC_STD.ALL in the beginning.
Second Question:
Once the division is don, how do I connect this output (dat_a_0) as an input to the PID module? Or rather how do I edit the PID module such that this bit can be included? I would later like to choose a setpoint and do the locking using PyRPL. Thanks!
The full adder code:
Code: Select all
--------------------------------------------------------------------------------
-- Author: fpgaSim123
--
-- Design Name: Adder
-- Project Name: Red Pitaya V0.94
-- Target Device: Red Pitaya STEMlab 125-14
-- Tool versions: Vivado 2020.1
-- Description: Input adder code
-- Sys Registers: 403_00000 to 403_fffff (uses MIMO PID register space)
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity adder is
port (
clk_i : in std_logic; -- bus clock
rstn_i : in std_logic; -- bus reset - active low
dat_a_i : in std_logic_vector(13 downto 0); -- input 1
dat_b_i : in std_logic_vector(13 downto 0); -- input 2
dat_a_o : out std_logic_vector(13 downto 0); -- output 1
-- dat_b_o : out std_logic_vector(13 downto 0); -- output 2 // disabled
sys_addr : in std_logic_vector(31 downto 0); -- bus address
sys_wdata : in std_logic_vector(31 downto 0); -- bus write data
sys_wen : in std_logic; -- bus write enable
sys_ren : in std_logic; -- bus read enable
sys_rdata : out std_logic_vector(31 downto 0); -- bus read data
sys_err : out std_logic; -- bus error indicator
sys_ack : out std_logic -- bus acknowledge signal
);
end adder;
architecture Behavioral of adder is
begin
adding: process(dat_a_i,dat_b_i)
begin
dat_a_o <= dat_a_i + dat_b_i ;
end process;
end Behavioral;
I would like to use the PID module for locking but I see that it accepts only one input. I would like to divide two signals (from in1 and in2), send the quotient as the input to the PID module where I choose a set point and attempt at lock the phase of an interferometer.