Averaging and repetition rate

Applications, development tools, FPGA, C, WEB
Post Reply
Posts: 7
Joined: Tue Aug 12, 2014 3:34 pm

Averaging and repetition rate

Post by diracdeltafunct » Tue Aug 12, 2014 3:56 pm

I am trying to test the noise and spur properties of the red pitaya for use as a digitizer in a device we build. In doing so I need to record up to 10 million signal acquisitions at the full record length of the device (similar to a standard digital storage oscilloscope). My end goal is to have the duty cycle of the red pitaya to be as high as possible ( minimum downtime between each 16k point acquisition) by accumulating each acquisition in the FPGA before transferring it to an external device for processing.

Before I worry about programming the FPGA, I am trying to test the internal noise properties by acquiring up to 10M averages by controlling the system externally though SSH [via python/sh scripts]. However, when I do this the duty cycle is very very low (1%). I have tried both streaming the data over SSH and piping the acquire output to a file (# acquire 16000 >some_iterator_name.txt). Currently using this method 10M averages would take several hours which might not work with our application.

Is there is a faster way in which I can do repetitive averaging like this as to increase the duty cycle for my testing purposes without having to spend a ton of time developing code?

Edit: To clarify we just want to quickly test if the noise properties are suited to our application as a test to see if we want to go further into development.

Crt Valentincic
Posts: 67
Joined: Wed May 28, 2014 12:15 pm

Re: Averaging and repetition rate

Post by Crt Valentincic » Wed Aug 13, 2014 2:19 pm

For a simple test, I would suggest you to try to use very simple version of acquire
program as is this one here.
When decimation is set to 64, this program performs continuous acquisition that fills circular buffer at 1.95MHz sample rate,
which is slow enough that can be continuously read by the CPU.
Notice that ADC still samples at 125MHz and ADC samples can also be averaged if this is enabled
through FPGA acquisition module register (g_osc_fpga_reg_mem->other = 1;).

Post Reply
jadalnie klasyczne ekskluzywne meble wypoczynkowe do salonu ekskluzywne meble tapicerowane ekskluzywne meble do sypialni ekskluzywne meble włoskie

Who is online

Users browsing this forum: No registered users and 3 guests