1) Error messages in FPGA make
Code: Select all
make[1]: Leaving directory `/home/emily/RedPitaya/FPGA/release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/device-tree_bsp_0'
make -C ahead/red_pitaya.sdk/SDK/SDK_Export/uboot_bsp_0/ -k all
make[1]: Entering directory `/home/emily/RedPitaya/FPGA/release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/uboot_bsp_0'
libgen -hw ../hw/system.xml\
-lp ../bsp_repos\
-pe ps7_cortexa9_0 \
-log libgen.log \
system.mss
libgen
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../hw/system.xml -lp ../bsp_repos -pe ps7_cortexa9_0
-log libgen.log system.mss
Staging source files.
Running DRCs.
#--------------------------------------
# uboot BSP DRC...
#--------------------------------------
Running generate.
#--------------------------------------
# uboot BSP generate...
#--------------------------------------
Not find correct clock frequency
/* Main Memory is ps7_ddr_0 */
FLASH doesn't exists
INFO automatic U-BOOT position = 0x1fc00000
Running post_generate.
Running execs_generate.
Finished building libraries
make[1]: Leaving directory `/home/emily/RedPitaya/FPGA/release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/uboot_bsp_0'
make -C image/ FPGA_TOOL=ahead -k all
make[1]: Entering directory `/home/emily/RedPitaya/FPGA/release1/fpga/image'
cp ../ahead/red_pitaya.runs/impl_1/red_pitaya_top.bit out/fpga.bit
cp: cannot create regular file ‘out/fpga.bit’: No such file or directory
make[1]: *** [bootbin] Error 1
cp ../ahead/red_pitaya.sdk/SDK/SDK_Export/device-tree_bsp_0/ps7_cortexa9_0/libsrc/device-tree_v0_00_x/xilinx.dts out/devicetree.dts
cp: cannot create regular file ‘out/devicetree.dts’: No such file or directory
make[1]: *** [devicetree] Error 1
make[1]: Target `all' not remade because of errors.
make[1]: Leaving directory `/home/emily/RedPitaya/FPGA/release1/fpga/image'
make: *** [image] Error 2
Code: Select all
make[3]: Leaving directory `/home/emily/RedPitaya/FPGA/release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/fsbl/Debug'
make[2]: Leaving directory `/home/emily/RedPitaya/FPGA/release1/fpga'
cp release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/fsbl/Debug/fsbl.elf /home/emily/RedPitaya/build/memtest.elf
cp release1/fpga/ahead/red_pitaya.runs/impl_1/red_pitaya_top.bit /home/emily/RedPitaya/build/fpga.bit
cp release1/fpga/ahead/red_pitaya.sdk/SDK/SDK_Export/device-tree_bsp_0/ps7_cortexa9_0/libsrc/device-tree_v0_00_x/xilinx.dts /home/emily/RedPitaya/build/devicetree.dts
patch /home/emily/RedPitaya/build/devicetree.dts release1/fpga/image/src/device_tree_ahead.patch
patching file /home/emily/RedPitaya/build/devicetree.dts
Hunk #1 succeeded at 150 (offset -6 lines).
Hunk #2 succeeded at 178 with fuzz 2 (offset -14 lines).
Hunk #3 FAILED at 390.
1 out of 3 hunks FAILED -- saving rejects to file /home/emily/RedPitaya/build/devicetree.dts.rej
make[1]: *** [install] Error 1
make[1]: Leaving directory `/home/emily/RedPitaya/FPGA'
make: *** [build/fpga.bit] Error 2